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White Rabbit Switch - Gateware
Commit 39cccfb9 authored by Maciej Lipinski's avatar Maciej Lipinski
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[SIM] make the top simulation work again

parent d315bf7b
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Showing with 12 additions and 7 deletions
modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd
View file @ 39cccfb9
...@@ -60,7 +60,7 @@ end wrsw_ljd_detect; ...@@ -60,7 +60,7 @@ end wrsw_ljd_detect;
architecture Behavioral of wrsw_ljd_detect is architecture Behavioral of wrsw_ljd_detect is
signal clk_divider : integer range 0 to g_clk_divider-1; signal clk_divider : integer range 0 to g_clk_divider;---1;
signal clk_en : std_logic; signal clk_en : std_logic;
signal bit_position : integer range 0 to g_pattern'length-1; signal bit_position : integer range 0 to g_pattern'length-1;
signal error_detected : std_logic; signal error_detected : std_logic;
......
testbench/scb_top/run.do
View file @ 39cccfb9
make -f Makefile # make -f Makefile
#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683 vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
......
top/bare_top/scb_top_sim.vhd
View file @ 39cccfb9
...@@ -189,7 +189,7 @@ begin -- rtl ...@@ -189,7 +189,7 @@ begin -- rtl
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
-- clk_sys_i => clk_sys_i, -- clk_sys_i => clk_sys_i,
clk_aux_i => clk_aux_i, clk_aux_i => clk_aux_i,
clk_ext_mul_i => '0', clk_ext_mul_i => "00",
clk_ext_mul_locked_i=> '1', clk_ext_mul_locked_i=> '1',
cpu_wb_i => cpu_wb_in, cpu_wb_i => cpu_wb_in,
cpu_wb_o => cpu_wb_out, cpu_wb_o => cpu_wb_out,
...@@ -224,7 +224,12 @@ begin -- rtl ...@@ -224,7 +224,12 @@ begin -- rtl
i2c_scl_i => i2c_scl_in, i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen, i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out, i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in i2c_sda_i => i2c_sda_in,
ljd_loopback_i => '0',
ljd_osc_freq_i => "000",
ljd_pll_miso_i => '0',
ljd_pll_locked_i=> '0'
); );
gen_phys : for i in 0 to g_num_ports-1 generate gen_phys : for i in 0 to g_num_ports-1 generate
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 39cccfb9
...@@ -348,8 +348,8 @@ package wrsw_top_pkg is ...@@ -348,8 +348,8 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic; clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic := '0'; clk_ext_mul_i : in std_logic_vector(1 downto 0) := (others=>'0');
clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0'); clk_ext_mul_locked_i : in std_logic := '0';
clk_sys_o : out std_logic; clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in; cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out; cpu_wb_o : out t_wishbone_slave_out;
......
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