Commit 1c33a80f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

wrsw_ext_board: synchronous reset for FSM

parent 78d3f242
...@@ -85,42 +85,44 @@ begin ...@@ -85,42 +85,44 @@ begin
FSM_INST : process (clk_sys_i) FSM_INST : process (clk_sys_i)
begin begin
if rst_n_i = '0' then if rising_edge(clk_sys_i) then
board_detected_o <= '0'; if rst_n_i = '0' then
fsm_state <= INIT; board_detected_o <= '0';
elsif rising_edge(clk_sys_i) then fsm_state <= INIT;
case fsm_state is else
when INIT => case fsm_state is
board_detected_o <= '0'; when INIT =>
bit_position <= 0; board_detected_o <= '0';
fsm_state <= WRITE_BIT; bit_position <= 0;
error_detected <= '0'; fsm_state <= WRITE_BIT;
error_detected <= '0';
when WRITE_BIT => when WRITE_BIT =>
loopback_o <= g_pattern(bit_position); loopback_o <= g_pattern(bit_position);
if (clk_en = '1') then if (clk_en = '1') then
fsm_state <= READ_BIT; fsm_state <= READ_BIT;
end if; end if;
when READ_BIT => when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then if (bit_position = g_pattern'length-1) then
fsm_state <= DONE; fsm_state <= DONE;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
end if;
else else
bit_position <= bit_position + 1; error_detected <= '1';
fsm_state <= WRITE_BIT; fsm_state <= DONE;
end if; end if;
else
error_detected <= '1';
fsm_state <= DONE;
end if;
when DONE => when DONE =>
board_detected_o <= not error_detected; board_detected_o <= not error_detected;
when others => when others =>
fsm_state <= INIT; fsm_state <= INIT;
end case; end case;
end if;
end if; end if;
end process; end process;
......
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