Commit 1c33a80f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

wrsw_ext_board: synchronous reset for FSM

parent 78d3f242
......@@ -85,42 +85,44 @@ begin
FSM_INST : process (clk_sys_i)
begin
if rst_n_i = '0' then
board_detected_o <= '0';
fsm_state <= INIT;
elsif rising_edge(clk_sys_i) then
case fsm_state is
when INIT =>
board_detected_o <= '0';
bit_position <= 0;
fsm_state <= WRITE_BIT;
error_detected <= '0';
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
board_detected_o <= '0';
fsm_state <= INIT;
else
case fsm_state is
when INIT =>
board_detected_o <= '0';
bit_position <= 0;
fsm_state <= WRITE_BIT;
error_detected <= '0';
when WRITE_BIT =>
loopback_o <= g_pattern(bit_position);
if (clk_en = '1') then
fsm_state <= READ_BIT;
end if;
when WRITE_BIT =>
loopback_o <= g_pattern(bit_position);
if (clk_en = '1') then
fsm_state <= READ_BIT;
end if;
when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then
fsm_state <= DONE;
when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then
fsm_state <= DONE;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
end if;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
error_detected <= '1';
fsm_state <= DONE;
end if;
else
error_detected <= '1';
fsm_state <= DONE;
end if;
when DONE =>
board_detected_o <= not error_detected;
when DONE =>
board_detected_o <= not error_detected;
when others =>
fsm_state <= INIT;
end case;
when others =>
fsm_state <= INIT;
end case;
end if;
end if;
end process;
......
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