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White Rabbit Switch - Gateware
Commit 0e9ae9d4 authored by José López Jiménez's avatar José López Jiménez
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Fixes on the timing scheme of the 18 port low jitter version 

Also mended some typos.
parent 3681f28d
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Showing with 132 additions and 82 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 0e9ae9d4
......@@ -435,8 +435,8 @@ begin -- rtl
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
slave_i => cnx_master_out(c_SLAVE_SPI_GM),
slave_o => cnx_master_in(c_SLAVE_SPI_GM),
desc_o => open,
pad_cs_o(0) => gm_pll_cs_n_o,
pad_sclk_o => gm_pll_sck_o,
......@@ -495,9 +495,9 @@ begin -- rtl
cpu_reset_n <= not gpio_out(2) and rst_n_i;
rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4);
gpio_in(5) <= ext_board_detected_i;
gpio_in(8 downto 6) <= ext_board_osc_freq_i;
gm_pll_reset_n_o <= gpio_out(4);
-- gpio_in(5) <= ext_board_detected_i;
-- gpio_in(8 downto 6) <= ext_board_osc_freq_i;
U_Main_DAC : gc_serial_dac
......
syn/scb_18ports/test_scb.xise
View file @ 0e9ae9d4
......@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
......@@ -1560,6 +1560,6 @@
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
top/bare_top/wrsw_top_pkg.vhd
View file @ 0e9ae9d4
......@@ -215,7 +215,7 @@ package wrsw_top_pkg is
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_db_i : in std_logic;
-- clk_ext_db_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -249,14 +249,14 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_board_detected_i: in std_logic;
-- ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
gm_pll_mosi_o : out std_logic;
gm_pll_miso_i : in std_logic;
gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic;
-- ext_board_detected_i: in std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 0e9ae9d4
This diff is collapsed.
top/scb_18ports/scb_top_synthesis.vhd
View file @ 0e9ae9d4
......@@ -233,8 +233,9 @@ architecture Behavioral of scb_top_synthesis is
signal clk_sys_startup : std_logic;
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal clk_dmtd_125 : std_logic;
signal clk_dmtd_125, clk_dmtd_tobufg, dmtd_pll_fb : std_logic;
signal pllout_clk_fb : std_logic;
signal pps_out : std_logic;
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "1.0ns";
......@@ -397,6 +398,8 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
begin
......@@ -498,8 +501,8 @@ begin
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_62mhz,
I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i);
I => gm_clk_62mhz_p_i,
IB => gm_clk_62mhz_n_i);
U_Buf_ext_clk10mhz : IBUFDS
generic map (
......@@ -507,8 +510,8 @@ begin
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_10MHz,
I => ext_clk_10mhz_p_i,
IB => ext_clk_10mhz_n_i);
I => gm_clk_10mhz_p_i,
IB => gm_clk_10mhz_n_i);
CLK_10MHZ_ext : BUFG
port map (
......@@ -518,23 +521,56 @@ begin
clk_10mhz <= ext_clk_10MHz_bufg;
clk_ext_mul <= ext_clk_62mhz;
U_Buf_CLK_DMTD : IBUFG
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => clk_dmtd_125,
I => fpga_clk_dmtd_i);
-- U_Buf_CLK_DMTD : IBUFG
-- generic map (
-- IOSTANDARD => "DEFAULT")
-- port map (
-- O => clk_dmtd_125,
-- I => fpga_clk_dmtd_i);
U_Buf_CLK_DMTD_DIV : BUFR
generic map(
BUFR_DIVIDE => "2")
port map (
I => clk_dmtd_125,
O => clk_dmtd,
I => fpga_clk_dmtd_i,
O => clk_dmtd_tobufg,
CE => '1',
CLR => '0');
U_CLK_DMTD_BUFG : BUFG
port map (
I => clk_dmtd_tobufg,
O => clk_dmtd);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
--U_DMTD_PLL : MMCM_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED",
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT_F => 8.0,
-- CLKFBOUT_PHASE => 0.000,
-- CLKOUT0_DIVIDE_F => 16.0, -- 62.5 MHz
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKIN1_PERIOD => 8.0,
-- REF_JITTER1 => 0.016)
-- port map (
-- CLKFBOUT => dmtd_pll_fb,
-- CLKOUT0 => clk_dmtd_tobufg,
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => open,
-- RST => '0',
-- PWRDWN => '0',
-- CLKFBIN => dmtd_pll_fb,
-- CLKIN1 => clk_dmtd_125); --actually 50 mhz yet
U_SYS_PLL : PLL_BASE
generic map (
......@@ -567,6 +603,7 @@ begin
RST => '0',
CLKFBIN => pllout_clk_fb,
CLKIN => clk_25mhz);
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
......@@ -637,13 +674,13 @@ begin
-- GTX PHYs
-------------------------------------------------------------------------------
clk_gtx(1 downto 0) <= (others => clk_gtx16_19);
clk_gtx(5 downto 2) <= (others => clk_gtx12_15);
clk_gtx(9 downto 6) <= (others => clk_gtx8_11);
clk_gtx(13 downto 10) <= (others => clk_gtx4_7);
clk_gtx(17 downto 14) <= (others => clk_gtx0_3);
clk_gtx(1 downto 0) <= (others => clk_gtx16_19); -- formerly two bufr
clk_gtx(5 downto 2) <= (others => clk_gtx12_15); -- formerly two bufr and two bufg
clk_gtx(9 downto 6) <= (others => clk_gtx8_11); -- formerly 4 bufg
clk_gtx(13 downto 10) <= (others => clk_gtx4_7); -- formerly 4 bufg
clk_gtx(17 downto 14) <= (others => clk_gtx0_3);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
-- generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
U_PHY : wr_gtx_phy_virtex6
......@@ -673,7 +710,7 @@ begin
rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-1 generate
......@@ -749,7 +786,7 @@ begin
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
pps_o => pps_o,
pps_o => pps_out,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
......@@ -789,6 +826,9 @@ begin
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => open);
-- Reverse PPS to correct hardware mishap in physical latch.
pps_o <= not pps_out;
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
......
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