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White Rabbit Switch - Gateware
Commit 3681f28d authored by José López Jiménez's avatar José López Jiménez
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Cleaned and adapted code for wr switch lj components

parent e278e934
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Showing with 363 additions and 511 deletions
wr-cores @ 39e1b531
Subproject commit 783cb73ca3dba2c2365065b0592e84d1892a5ddc
Subproject commit 39e1b5319caaefd36a593b7d11a29805290da2f8
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 3681f28d
......@@ -60,12 +60,6 @@ entity wrsw_rt_subsystem is
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- WRS Low jitter daughterboard
clk_ext_db_i : in std_logic;
ext_board_detected_i: in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
rst_n_i : in std_logic;
rst_n_o : out std_logic;
......@@ -127,12 +121,12 @@ entity wrsw_rt_subsystem is
pll_reset_n_o : out std_logic;
-- WRS Low jitter daughterboard AD9516
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
gm_pll_mosi_o : out std_logic;
gm_pll_miso_i : in std_logic;
gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic;
-- Debug
......@@ -164,7 +158,6 @@ architecture rtl of wrsw_rt_subsystem is
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_db_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -246,7 +239,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
constant c_SLAVE_SPI_GM : integer := 8;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -370,10 +363,9 @@ begin -- rtl
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_db_i => clk_ext_db_i,
pps_csync_p1_i => pps_csync,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
dac_dmtd_load_o => dac_dmtd_load,
......@@ -446,10 +438,10 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open,
pad_cs_o(0) => ext_pll_cs_n_o,
pad_sclk_o => ext_pll_sck_o,
pad_mosi_o => ext_pll_mosi_o,
pad_miso_i => ext_pll_miso_i);
pad_cs_o(0) => gm_pll_cs_n_o,
pad_sclk_o => gm_pll_sck_o,
pad_mosi_o => gm_pll_mosi_o,
pad_miso_i => gm_pll_miso_i);
U_GPIO : xwb_gpio_port
generic map (
......
top/bare_top/scb_top_bare.vhd
View file @ 3681f28d
......@@ -72,16 +72,19 @@ entity scb_top_bare is
-- Startup 25 MHz clock (from onboard 25 MHz oscillator)
clk_startup_i : in std_logic;
-- 62.5 MHz timing reference (from the AD9516 PLL output QDRII_CLK)
-- 62.5 MHz timing reference (from the AD9516 PLL)
clk_ref_i : in std_logic;
-- 62.5+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
clk_dmtd_i : in std_logic;
-- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
-- for re-phasing the 10 MHz input as well as clocking the
-- Ext clk: 10 MHz external reference from SMC port
clk_ext_i : in std_logic;
-- Aux clock (from the swcore_pll)
clk_aux_i : in std_logic;
-- 62.5 MHz clock generated from external 10 MHz in AD9516
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
......@@ -117,11 +120,6 @@ entity scb_top_bare is
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-- WRS Low jitter daughterboard (db) external clock
clk_ext_db_i : in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
......@@ -134,12 +132,12 @@ entity scb_top_bare is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
gm_pll_mosi_o : out std_logic;
gm_pll_miso_i : in std_logic;
gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -527,10 +525,8 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK AND UNSUITABLE FOR v3.5
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_db_i => clk_ext_db_i,
ext_board_detected_i => ext_board_detected_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -563,7 +559,7 @@ begin
tm_cycles_o => tm_cycles,
tm_time_valid_o => tm_time_valid,
pll_status_i => '0',
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......@@ -571,14 +567,13 @@ begin
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
gm_pll_mosi_o => gm_pll_mosi_o,
gm_pll_miso_i => gm_pll_miso_i,
gm_pll_sck_o => gm_pll_sck_o,
gm_pll_cs_n_o => gm_pll_cs_n_o,
gm_pll_sync_n_o => gm_pll_sync_n_o,
gm_pll_reset_n_o => gm_pll_reset_n_o,
ext_board_osc_freq_i => ext_board_osc_freq_i,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 3681f28d
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top/scb_18ports/scb_top_synthesis.vhd
View file @ 3681f28d
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