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Created with Raphaël 2.2.018Nov12Aug43128Jul1420May548Apr13Nov230Oct26Aug1914Jul139732130Jun2928261693226May8528Apr2330Mar262522211817219Feb181327Jan9Dec5317Oct1519Sep167Aug422Jul1726Jun2518179Apr20Mar181420Feb1918171465429Jan17Nov151413121087653131Oct3027252423222120171516Sep1211109530Aug2721201698652131Jul292422181756Jun530May242111109729Apr2524151228Mar2726252422191815141312118754322Feb18161411765124Jan18171611920Dec181714121154330Nov987631Oct98414Sep1320Aug31Jul27262418171325Jun22725May2243227Apr26252019181716133229Marswcore: swc_ll_read_data_validate supports generic number of write interfacesswcore: adding Switched-Multiported-RAM from githubswcore: move some constants to swcore_pkg, add shared arrays for ll pagesswcore: by default reserve 256 pages in MPM for HP trafficswcore: adding wishbone registers to export MPM statustestbench: adding testbench for NIC b/w throttlingwrsw_nic: fix indentation in *.wb filewrsw_nic: fix *.wb file to provide tx/rx descriptor fields for softwarewrsw_nic: adding enable bit for b/w throttlingwrsw_nic: Random Early Detection for b/w throttlingwrsw_nic: bw throttling, no throttling yetadding rmon events in NIC for per-port tx framesFixes make to wr-nic use wrpc3.0.wrnic_wrpc3wrnic_wrpc3[top testbench] added test for dropping of nonHP when HP is in output queue (mimics the setup I have in the lab)ML-PhD-HP-testsML-PhD-HP-testsadding missing clk_ext_mul_locked_i so that the simulation does not complain[top testbench] added test case for PhD[swcore] Drop non-hp frames when traffic recognized as hp (critical) is in output queued.[top simulation]: make simulation work with the newly added phy_rdy signalMask rtu response for the ports that are downadded descriptionML-PTP-support-…ML-PTP-support-150317bare_top/gen_sdbsyn.py: don't crash when git username is not setremoving building.txt, now all the information is on wiki pagesadding missing clk_ext_mul_locked_i so that the simulation does not complainupdate building.txt for v4.2 releasehwiu: update HDL info for v4.2 releasewr-switch-sw-v4.2wr-switch-sw-v4.2swcore/mpm: prevent premature frame terminationwrsw_nic: count acks only when frame is being senthwiu: update info for v4.2wr-switch-sw-v4…wr-switch-sw-v4.2-rc2feed softpll with locked signals from plls multiplying ext. 10MHz in to 62.5MHzhwiu: update info for v4.2bare_top: update gw version reported by HWIU to 4.2scb_18ports: relaxing dmtd clock maxskew constraintwrsw_pstats: split L2 counting into two modules to improve timing closure for 18-port WRSwrsw_pstats: make rd_port type unsigned to save conversion everytime it's usedswcore-cleanup: move obsolete files to a separate directory10mhz_gen: fix output level of the generated signal10mhz_gen: fix potential bug, reset oserdes with pll locked signalscb_top_bare: remove old debug signalstrivial fix of missing clk_ext_mul_i signal and wrong comamodules/watchdog: make resetting sequence much longer to be sure we ack everything what is still in the buffers