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Created with Raphaël 2.2.05Jun28May27231413109830Apr11Mar8656Dec29Nov262015Sep13119748Jun20Dec28Nov252322211812Aug43128Jul1420May548Apr13Nov230Oct26Aug1914Jul139732130Jun2928261693226May8528Apr2330Mar262522211817219Feb181327Jan9Dec5317Oct1519Sep167Aug422Jul1726Jun2518179Apr20Mar181420Feb1918171465429Jan17Nov151413121087653131Oct3027252423222120171516Sep1211109530Aug2721201698652131Jul292422181756Jun530May242111109729Apr2524151228Mar2726252422191815141312118754322Feb18161411765124Jan18171611920Dec181714121154330Nov987631Oct98414Sep1320Aug31Jul27262418171325Jun22725May2243add bit to control WRS 1-PPS in terminationAdded holdover expansion pins and changed GM PLL pinoutPinout changes for low jitter clockingMerge remote-tracking branch 'ohwr/wrs-v5.1' into hm-wrsfl-lowjitterSolved typo in 8-port constraints file and reverted to older hdlmakeChanged submodule path post-migrationMerge branch 'greg-mirroring' into proposed_masteradd port mirroring for NIC/CPU originated trafficpass NIC originated RTU decisions through RTU modulefix simulation for modern Modelsim versionsfix simulation after reset changes in wr-coresupdate wr-cores to fix simulation after nic and txtsu move update wr-cores.update general-cores change 8ports to 2ports to reduce compiling time.move wrsw_txtsu to wr-cores repositorymove wrsw_nic to wr-cores repositorywrsw_pstats: fix Manifest for more picky hdlmakeMerge branch 'wrs-pts-v1.0' into proposed_masterupdate submodules after ohwr migration sort out the ucf file for 18port project. Comment out "clk_sys_dbg_o" in ucf/top update ise project file.update submodules to include preamble shrinkage support Change the DDMTD source from ext VCXO to cascaded PLL.hm-wrsfl-ddmtdhm-wrsfl-ddmtdadd bit to control WRS 1-PPS in termination Revert some small modification to make it follow the main branch. Modify the lowjitter function from the second ext clk to the normal ext clk. Add Low jitter function based on mattia's work. try to merge the code from low jitter board.Prepared for PTS buildwrs-pts-v1.0wrs-pts-v1.0Modified synthesis configuration for 18ports buildUpdated wr-cores for external boardModified contrains for 8 portsModifed Manifests to build correctly the project fileAdded support for the external boardAdded a powerdown line to shutdown the noisy MMCMs when external PLL is detectedModifed constrains for WRS low jitter daughterboardAdded module to check the presence of the external boardModified contrain file for 8 ports