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Created with Raphaël 2.2.020Aug191514131296Jul112Jun11528May27231413109830Apr11Mar8656Dec29Nov262015Sep13119748Jun20Dec28Nov252322211812Aug43128Jul1420May548Apr13Nov230Oct26Aug1914Jul139732130Jun2928261693226May8528Apr2330Mar262522211817219Feb181327Jan9Dec5317Oct1519Sep167Aug422Jul1726Jun2518179Apr20Mar181420Feb1918171465429Jan17Nov151413121087653131Oct3027252423222120171516Sep1211109530Aug2721201698652131Jul292422181756Jun530May242111109729Apr2524151228Mar2726252422191815141312118754322Feb18161411765124Jan18171611920Dec181714121154330Nov987631Oct98414Sep1320Aug31Jul2726241817Merge branch 'greg-low-jitter' into proposed_masterljd: use ad9516 lock signal and reset it with ext_pll_reset bitadd _ljd_ prefix to everything Low-Jitter Daughterboard relatedljd: move daughterboard detection inside rt subsystemwrs_ljd: use bufr for 8port like to 18portsoftpll: use generic to define number of ext channelsrename ext_board_check to wrsw_ext_board_checkremove unused I/Os and assign default valueswrsw_ext_board: synchronous reset for FSMwrsw_ext_board: fix formatting, no technical changert_subsystem: add generic for low jitter daughterboard supportModified synthesis configuration for 18ports buildModified constraints for low-jitter daughterboardUpdated wr-cores for external boardModifed Manifests to build correctly the project fileAdded support for the external boardAdded a powerdown line to shutdown the noisy MMCMs when external PLL is detectedAdded module to check the presence of the external boardMerge remote-tracking branch 'ohwr/wrs-v5.1' into hm-wrsflhm-wrsflhm-wrsfl Merge remote-tracking branch 'origin/hm-wrsfl-lowjitter' into hm-wrslj-ptshm-wrslj-ptshm-wrslj-pts add NET TIG constraints in ucf for easy compilation.hm-wrsljhm-wrsljCleaned and adapted code for wr switch lj components add clk_ext_10m_i pin. update .gitmodules url.add bit to control WRS 1-PPS in terminationAdded holdover expansion pins and changed GM PLL pinoutPinout changes for low jitter clockingMerge remote-tracking branch 'ohwr/wrs-v5.1' into hm-wrsfl-lowjitterSolved typo in 8-port constraints file and reverted to older hdlmakeChanged submodule path post-migrationMerge branch 'greg-mirroring' into proposed_masteradd port mirroring for NIC/CPU originated trafficpass NIC originated RTU decisions through RTU modulefix simulation for modern Modelsim versionsfix simulation after reset changes in wr-coresupdate wr-cores to fix simulation after nic and txtsu move update wr-cores.update general-cores change 8ports to 2ports to reduce compiling time.move wrsw_txtsu to wr-cores repository