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Created with Raphaël 2.2.09Sep30Aug282220724Jul2322171221Jun2010729May282726222117161514131211107229Apr22181711109420Mar1912Dec11954130Nov2928271514131Oct28Sep17May19Jan1321Dec2017Jul18Jan1513118614Aug29Jul72130Jun27May15146Apr320Jan720Dec191793Sep30Aug20191514131296Jul112Jun11528May27231413109830Apr11Mar8656Dec29Nov262015Sep13119748Jun20Dec28Nov252322211812Aug43128Jul1420May548Apr13Nov230Oct26Aug1914Jul139732130Jun2928261693226May8528Apr2330Mar262522211817219Feb181327Jan9Dec5317Oct1519Sep167Aug422Jul1726Jun2518179Apr20Mar181420Feb1918171465429Jan17Nov151413121087653131Oct3027252423222120171516Sep1211109530Aug2721201698652131Jul2924221817move urv boot regs back to rts xbarupdate general-cores, hence reinstate dac_seladd urv-core to 18p Manifestupdates to use wrpc-v5.0 corescorrect sdb mbox size, move urvboot regs to main xbarupdate submodulesadd urv to wrsv3[sim] fix reset problem in the endpointsfix_simfix_sim[sim] align and update inputs and outputs of the top to make sim work[sim] fix typo[sim] fix out-of-range error.update link and activity led mappingFix images in .ohwr.yamlAdd .ohwr.yamlupdated 10mhz clk gen for us+, added initial pps delayUpdate gateware for Safran's WRS-LJ v2.0 hardwarev7.0.1-devv7.0.1-devMerge branch 'wrs-v4-dev' of https://ohwr.org/project/wr-switch-hdl into wrs-v4-devun-invert uart tx/rx, generate .bin bitstreamupdate scb_top_bare component in line with entity changesconnect pps in bare top, no delay for nowafcz generate .bin bitstreamafcz: connect ppsafcz: connect ppsconnect switching coreupdate sfp mappingMerge branch 'wrs-v4-dev' of https://ohwr.org/project/wr-switch-hdl into wrs-v4-devadd pullup to hmc_sdataupdate ps refclk freqRevert "DDMTD: disable reverse option, it needs to be coupled with relevant changes to wrpc-sw"wr-switch-sw-v7…wr-switch-sw-v7.0_prop_v6.0_ddmtd_reverse_trueRevert "DDMTD: disable reverse option, it needs to be coupled with relevant changes to wrpc-sw"wr-switch-sw-v7.0wr-switch-sw-v7.0[ise] optimizing/changing parameters to meet constraintswr-switch-sw-v7…wr-switch-sw-v7.0_optimized_ise_properties[ise] process properties as in v5.0[ise] configuration exactly as in v6.0wr-switch-sw-v7…wr-switch-sw-v7.0_prop_v6.0[ise] clean up setting of propertiesManifest.py: fix ngc error for new hdlmaketop/bare_top/gen_sdbsyn.py: update to python3top/bare_top/gen_sdbsyn.py: update to python3.gitlab-ci.yml: use another docker image for synthesis[ise] change "Use RLOC constraint"ML-test-prop-v5…ML-test-prop-v5-optimize[ise] configuration exactly as in v6.0wr-switch-sw-v6…wr-switch-sw-v6.0-CI