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Created with Raphaël 2.2.05Dec4330Nov987631Oct98414Sep1320Aug31Jul27262418171325Jun22725May2243227Apr26252019181716133229Mar261918161513121198724Feb232221131287222Jan19171211109Dec18Apr1218Mar9Dec7532129Nov2725242322211915229Oct1425Aug1316Jul15Jun9TRU and RTUex - integration with new endpoint: changing singals appropriately in TRU and scb_topRTUex: fixing mirroring bug. Mirror destination port disabled when mirror_dst_mask set but mirroring disabled. Also, small debugging/display change to wr-coresTRU and RTUex: integrating TRU/RTUex with new endpoints - seems to be workingMerge branch 'TRUandRTU' of ohwr.org:white-rabbit/wr-switch-hdl into TRUandRTUTRUandRTUx: small modification to run.doTRUandRTUTRUandRTUMerge branch 'TRUandRTU' of ohwr.org:white-rabbit/wr-switch-hdl into TRUandRTUTRUandRTUex: adding uncommited (forgot) filesTRU: associating submodules with the module. This is the TRUandRTUeX version working with old endpoint. commit before moving to new endpoint (changed by Tom, added VLANs, injection, killing by me)generalized simulation, added few scenarios to test different features/functionalitiesRTUex: fixed bugs in mirroring, updated descriptionTRU: testbench update: enabling easier setup of different usecases for testing, debugging RTU driverTRU: version upgradeTRU: cosmetic changes to pattern choiceTRU: modified TRU table lookup to skip invalid entriesTRU: changed the way port status is seen by RTU/TRU - now port is seen as down also if it is disabledTRU: added simulation of a network of 3 WR switches (scb_to) - firt working versionm needs further workTRU: simple functionality of TRU (switching to backup ports) works on simulationTRU: endpoint with added ctrl signal which enables to kill (physically) the linkTRU: adapting simulation to changes in the endpoint (addition of ctrl for killing link). Also, hacking the simulation to be able to simulate link-down (sync lost) caseTRU: correcting endpointRTUeX: Initialization of control signal (with zeros)RTUeX: added fast dropping due to the fact that incoming frame does not belong to VLANRTUex: synthesis stuff for resource-optimized fast-match added RTUTRUandRTU-optim…TRUandRTU-optimizedRTUex: fast_match optimized for resources (RR-arbitrated access and pipelined for all ports)RTUeX: synthesis top level integrationRTUex: integration with top level scp_top_bareRTUeX: first kind-of-working version of the RTUeXtended: optimizing RTU for determinism (quick match/fast forward) and adding interace with TRUTRU: some more top-integrationtrutruTRU: integrating TRU into switch top entityTRU: connected RTU with TRU -- needed to add signals to RTU (just dummy assigment in RTU, need further implementation)TRU: bugfix: wrong order of port swapping/transitioningTRU: added modest comments to the code, some description, doing a bit of cleaningTRU: added TRU module to scb_top_bare and scb_top testbench (TRU does not interface other modules, except for WB interconnect for configuration). Added simple TRU configuration to the main simulationTRU: fixed bug outputQueuePause maskTRU: changed configuration WB I/F to pipelined and byte (as in other switch modules)TRU: sythesis ISE projectTRU: fixing bugs preventing from sythesis, test-sythesizing moduleTRU: adding first (working-on-simulation) version of the Topology Resolution Module with simple and basic testbenches in SystemVerilogscb_top sim: fixed config of RTUwrsw_txtsu: moved t_txtsu_timestamp structure definition to endpoint_pkg in wr_endpoint (wr-hdl)