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Created with Raphaël 2.2.07Jan20Dec191793Sep30Aug20191514131296Jul112Jun11528May27231413109830Apr11Mar8656Dec29Nov262015Sep13119748Jun20Dec28Nov252322211812Aug43128Jul1420May548Apr13Nov230Oct26Aug1914Jul139732130Jun2928261693226May8528Apr2330Mar262522211817219Feb181327Jan9Dec5317Oct1519Sep167Aug422Jul1726Jun2518179Apr20Mar181420Feb1918171465429Jan17Nov151413121087653131Oct3027252423222120171516Sep1211109530Aug2721201698652131Jul292422181756Jun530May242111109729Apr2524151228Mar2726252422191815141312118754322Feb18161411765124Jan18171611920Dec181714121154330Nov987631Oct98414Sep1320Augpstats: more registers to improve timingMerge branch 'joselj-ljwrs-dev' of bitbucket.org:sevensols/wr-switch-hdl into joselj-ljwrs-devIntegrated new I2C sensor and defined interface with expansion boardThe FPGA REF CLK is now connected to the output 5 of the AD9516 (instead of 8)add project file for releasepstats: add registers to improve timinglpd: update wr-cores for chicken-bits and rx synchronizerFixes on the timing scheme of the 18 port low jitter versionMerge branch 'greg-lpd-rebased' into proposed_masterfix low-jitter constraints after rebaselow phase drift calibration: cleanup 8-port versioncleanup low phase drift calibration interfacert_subsystem: add external samplers for port that are not calibrated for low phase driftlow phase drift calibration only for 12 portstop: manual control of TX/RX clock buffers for PHYs through genericsconstraining tx_out clock produced by GTX_LPphy determinism for 18-port versionMigrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...top/scb_8ports: 8-port PoC firmware with deterministic V6 transceiver configtop/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcorewrsw_rt_subsystem: allow externally sampled RX clocks (DDMTD inside the PHY module)update wr-cores: low-jitter support merged to proposed_masterMerge branch 'greg-low-jitter' into proposed_masterljd: use ad9516 lock signal and reset it with ext_pll_reset bitadd _ljd_ prefix to everything Low-Jitter Daughterboard relatedljd: move daughterboard detection inside rt subsystemwrs_ljd: use bufr for 8port like to 18portsoftpll: use generic to define number of ext channelsrename ext_board_check to wrsw_ext_board_checkremove unused I/Os and assign default valueswrsw_ext_board: synchronous reset for FSMwrsw_ext_board: fix formatting, no technical changert_subsystem: add generic for low jitter daughterboard supportModified synthesis configuration for 18ports buildModified constraints for low-jitter daughterboardUpdated wr-cores for external boardModifed Manifests to build correctly the project fileAdded support for the external boardAdded a powerdown line to shutdown the noisy MMCMs when external PLL is detectedAdded module to check the presence of the external board