Hm proposed master

See merge request !1

  1. add pll_status_i clock period constraints
  2. correct the TNM_NET name of rx_rec_clk_bufin.

rather than differential signal for 10M input.

    There are three types of wrs: normal wrs(mark as wrs), wrs with LJD
(mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ).
    lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ.
    lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD.
        lj_osc_freq_i=111 means WRSLJ.
        lj_osc_freq_i=others means WRS-LJD.

    lj_osc_freq_i[2 downto 0] need to be pulled up.

Possible through the combination of global and regional clocks. Cannot
have it for all ports because we don't have enough global/regional clock
nets in virtex-6.

Tomasz Wlostowski authored 6 years ago and Grzegorz Daniluk committed 5 years ago

Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...

Tomasz Wlostowski authored 6 years ago and Grzegorz Daniluk committed 5 years ago

top/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcore

Less code duplication in scb_8ports and scb_18ports top hdl.