[v4-dev] endpoint: tx-untagging bugfix

wr-cores @ 6b584ab0

-Subproject commit 67cd9ce053e3b3a43f0f4d29b1b03bb5ec61861f
+Subproject commit 6b584ab02828be266131fd7d3e42fb58c617ee98

testbench/scb_top/main.sv

@@ -199,6 +199,7 @@ module main;
    integer g_enable_WRtime                  = 0;
    integer g_tatsu_config                   = 0;
    integer g_fw_to_cpu_scenario             = 0;
+   integer g_set_untagging                  = 0;
    int lacp_df_hp_id                        = 0;
    int lacp_df_br_id                        = 2;
    int lacp_df_un_id                        = 1;
@@ -1164,7 +1165,7 @@ module main;
    * quick forward/block massage detection and action 
    * 
    **/
- ///*
+ /*
   initial begin
     portUnderTest        = 18'b000000000000000000;
     g_tru_enable         = 1;
@@ -1186,8 +1187,29 @@ module main;
     mc.logic2(25, 1, PFilterMicrocode::MOV, 0);    
     mc.logic2(26, 1, PFilterMicrocode::MOV, 0);    
     
+  end
+*/
+ /** ***************************   test scenario 38  ************************************* **/ 
+  /*
+   * tagging/untagging test
+   **/
+ //*
+  initial begin
+    portUnderTest        = 18'b000000000000000111;   
+    
+    qmode                = 0;//access
+    pvid                 = 1;//tagging vlan
+    g_is_qvlan           = 0; //send VLAN-tagged frames
+    g_do_vlan_config     = 1; //enable vlan confgi
+    g_set_untagging      = 1; // set pre-defined untagging config (untag VIDs:0 - 10)
+                         // tx  ,rx ,opt
+    trans_paths[0]       = '{0  ,17 , 0 };
+    trans_paths[1]       = '{1  ,16 , 0 };
+    trans_paths[2]       = '{2  ,15 , 0 };
+
   end
 //*/
+
 //////////////////////////////////////////////////////////////////////////////////////////////
 //////////////////////////////////////////////////////////////////////////////////////////////
 //////////////////////////////////////////////////////////////////////////////////////////////
@@ -1562,7 +1584,7 @@ module main;
    
 
    task automatic init_ports(ref port_t p[$], ref CWishboneAccessor wb);
-      int i;
+      int i,j;
       
       for(i=0;i<g_num_ports;i++)
         begin
@@ -1586,6 +1608,12 @@ module main;
              ep.pause_config( 1/*txpause_802_3*/, 1/*rxpause_802_3*/, 0/*txpause_802_1q*/, 0/*rxpause_802_1q*/);
            else if(g_pause_mode == 2)
              ep.pause_config( 1/*txpause_802_3*/, 1/*rxpause_802_3*/, 1/*txpause_802_1q*/, 1/*rxpause_802_1q*/);
+           
+           if(g_set_untagging == 1)
+           begin
+             for(j=0;j<10; j++)
+               ep.vlan_egress_untag(j,1);
+           end
            tmp.ep = ep;
            tmp.send = EthPacketSource'(DUT.to_port[i]);
            tmp.recv = EthPacketSink'(DUT.from_port[i]);

testbench/scb_top/simdrv_wr_endpoint.svh

@@ -9,14 +9,30 @@ class CSimDrv_WR_Endpoint;
 
    protected CBusAccessor m_acc;
    protected uint64_t m_base;
+   protected uint16_t untag_tab[256];
    
    function new(CBusAccessor acc, uint64_t base);     
+      int i;
       m_acc   = acc;
       m_base  = base;
+//       for(i=0;i<10;i++)
+//         untag_tab[i]=0;
    endfunction // new
 
    task vlan_egress_untag(int vid, int untag);
-      m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
+      uint64_t wval=0;
+      if(untag>0)
+        untag_tab[(vid>>4)] = untag_tab[(vid>>4)] |  (1<<('h000F & vid));
+      else
+        untag_tab[(vid>>4)] = untag_tab[(vid>>4)] & ! (1<<('h000F & vid));
+      
+      wval = (untag_tab[(vid>>4)] << 10) | ('h000003FF & (vid>>4));
+      
+      $display("[vlan_egress_untag], write offset: %d, data: 0x%x (val=0x%x)", 
+      (vid>>4),untag_tab[(vid>>4)], wval);      
+      m_acc.write(m_base + `ADDR_EP_VCR1, wval);
+      
+   //   m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
    endtask // vlan_egress_untag
 
    task vcr1_buffer_write(int is_vlan, int addr, uint64_t data);