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Commit cf13b090 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top/scb_test: top module (6 ports, no swcore yet)

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top/scb_test/Manifest.py 0 → 100644
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View file @ cf13b090
files = ["test_scb.vhd", "test_scb.ucf", "wb_cpu_bridge.vhd","wrsw_components_pkg.vhd"];
modules = { "local" : [ "../../" ] };
top/scb_test/test_scb.ucf 0 → 100644
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NET "sys_rst_n_i" LOC="M10";
# CLK
NET "fpga_clk_25mhz_p_i" LOC=K24;
NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_sys_p_i" LOC=A10;
NET "fpga_clk_sys_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
NET "cpu_wr_n_i" LOC="M25";
NET "cpu_rd_n_i" LOC="J31";
NET "cpu_bs_n_i<0>" LOC="J30";
NET "cpu_bs_n_i<1>" LOC="P29";
NET "cpu_bs_n_i<2>" LOC="H30";
NET "cpu_bs_n_i<3>" LOC="J34";
NET "cpu_nwait_o" LOC="R26";
NET "cpu_irq_n_o" LOC="AC24";
NET "cpu_addr_i<18>" LOC="M28";
NET "cpu_addr_i<17>" LOC="M30";
NET "cpu_addr_i<16>" LOC="C32";
NET "cpu_addr_i<15>" LOC="L31";
NET "cpu_addr_i<14>" LOC="L25";
NET "cpu_addr_i<13>" LOC="B33";
NET "cpu_addr_i<12>" LOC="B32";
NET "cpu_addr_i<11>" LOC="C33";
NET "cpu_addr_i<10>" LOC="L26";
NET "cpu_addr_i<9>" LOC="H32";
NET "cpu_addr_i<8>" LOC="G32";
NET "cpu_addr_i<7>" LOC="E32";
NET "cpu_addr_i<6>" LOC="F30";
NET "cpu_addr_i<5>" LOC="D31";
NET "cpu_addr_i<4>" LOC="L28";
NET "cpu_addr_i<3>" LOC="E33";
NET "cpu_addr_i<2>" LOC="J27";
NET "cpu_addr_i<1>" LOC="G31";
NET "cpu_addr_i<0>" LOC="D32";
#NET "cpu_addr_i<1>" LOC="H30";
#NET "cpu_addr_i<0>" LOC="J30";
NET "cpu_data_b<31>" LOC="T26";
NET "cpu_data_b<30>" LOC="R28";
NET "cpu_data_b<29>" LOC="R29";
NET "cpu_data_b<28>" LOC="N34";
NET "cpu_data_b<27>" LOC="P34";
NET "cpu_data_b<26>" LOC="P25";
NET "cpu_data_b<25>" LOC="L34";
NET "cpu_data_b<24>" LOC="R32";
NET "cpu_data_b<23>" LOC="R27";
NET "cpu_data_b<22>" LOC="P27";
NET "cpu_data_b<21>" LOC="P26";
NET "cpu_data_b<20>" LOC="K34";
NET "cpu_data_b<19>" LOC="M31";
NET "cpu_data_b<18>" LOC="R31";
NET "cpu_data_b<17>" LOC="N30";
NET "cpu_data_b<16>" LOC="N25";
NET "cpu_data_b<15>" LOC="L33";
NET "cpu_data_b<14>" LOC="K31";
NET "cpu_data_b<13>" LOC="K29";
NET "cpu_data_b<12>" LOC="K33";
NET "cpu_data_b<11>" LOC="J29";
NET "cpu_data_b<10>" LOC="K32";
NET "cpu_data_b<9>" LOC="M32";
NET "cpu_data_b<8>" LOC="J32";
NET "cpu_data_b<7>" LOC="C34";
NET "cpu_data_b<6>" LOC="K28";
NET "cpu_data_b<5>" LOC="G30";
NET "cpu_data_b<4>" LOC="D34";
NET "cpu_data_b<3>" LOC="B34";
NET "cpu_data_b<2>" LOC="H33";
NET "cpu_data_b<1>" LOC="J26";
NET "cpu_data_b<0>" LOC="A33";
NET "pps_i" LOC="J25";
NET "pps_o" LOC="U23";
NET "dac_helper_sync_n_o" LOC="AD17";
NET "dac_helper_sclk_o" LOC="AC15";
NET "dac_helper_data_o" LOC="AH17";
NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="AE18";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="AG31";
NET "uart_rxd_i" LOC="AC25";
NET "clk_en_o" LOC="AD16";
NET "clk_sel_o" LOC="AK17";
NET "gtx0_3_clk_n_i" LOC="AK5";
NET "gtx0_3_clk_p_i" LOC="AK6";
NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx4_7_clk_n_i" LOC="AD5";
NET "gtx4_7_clk_p_i" LOC="AD6";
NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx_rxp_i[0]" LOC="AP5";
NET "gtx_rxn_i[0]" LOC="AP6";
NET "gtx_txp_o[0]" LOC="AP1";
NET "gtx_txn_o[0]" LOC="AP2";
NET "gtx_rxp_i[1]" LOC="AM5";
NET "gtx_rxn_i[1]" LOC="AM6";
NET "gtx_txp_o[1]" LOC="AN3";
NET "gtx_txn_o[1]" LOC="AN4";
NET "gtx_rxp_i[2]" LOC="AL3";
NET "gtx_rxn_i[2]" LOC="AL4";
NET "gtx_txp_o[2]" LOC="AM1";
NET "gtx_txn_o[2]" LOC="AM2";
NET "gtx_rxp_i[3]" LOC="AJ3";
NET "gtx_rxn_i[3]" LOC="AJ4";
NET "gtx_txp_o[3]" LOC="AK1";
NET "gtx_txn_o[3]" LOC="AK2";
NET "gtx_rxp_i[4]" LOC="AG3";
NET "gtx_rxn_i[4]" LOC="AG4";
NET "gtx_txp_o[4]" LOC="AH1";
NET "gtx_txn_o[4]" LOC="AH2";
NET "gtx_rxp_i[5]" LOC="AF5";
NET "gtx_rxn_i[5]" LOC="AF6";
NET "gtx_txp_o[5]" LOC="AF1";
NET "gtx_txn_o[5]" LOC="AF2";
NET "gtx_sfp_tx_dis_o[0]" LOC="AD29";
NET "gtx_sfp_tx_dis_o[1]" LOC="AA29";
NET "gtx_sfp_tx_dis_o[2]" LOC="AC29";
NET "gtx_sfp_tx_dis_o[3]" LOC="AD31"; #GPIO30
NET "gtx_sfp_tx_dis_o[4]" LOC="AC28"; #GPIO33
NET "gtx_sfp_tx_dis_o[5]" LOC="AG32"; #GPIO36
NET "led_link_o[0]" LOC="AA26"; #GPIO14
NET "led_link_o[1]" LOC="AC30"; #GPIO13
NET "led_link_o[2]" LOC="AA31"; #GPIO11
NET "led_link_o[3]" LOC="AA34"; #GPIO9
NET "led_link_o[4]" LOC="AB33"; #GPIO7
NET "led_link_o[5]" LOC="AC33"; #GPIO5
NET "led_act_o[0]" LOC="AA28"; #GPIO15
NET "led_act_o[1]" LOC="AB30"; #GPIO12
NET "led_act_o[2]" LOC="AA33"; #GPIO10
NET "led_act_o[3]" LOC="AB32"; #GPIO8
NET "led_act_o[4]" LOC="AC34"; #GPIO6
NET "led_act_o[5]" LOC="AD34"; #GPIO4
top/scb_test/test_scb.vhd 0 → 100644
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top/scb_test/wb_cpu_bridge.vhd 0 → 100644
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------------------------------------------------------------------------------
-- Title : Atmel EBI asynchronous bus <-> Wishbone bridge
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-09-13
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: An interface between AT91SAM9x-series ARM CPU External Bus Interface
-- and FPGA-internal Wishbone bus:
-- - does clock domain synchronisation
-- - provides configurable number of independent WB master ports at fixed base addresses
-- TODO:
-- - implement write queueing and read prefetching (for speed improvement)
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_cpu_bridge is
generic (
g_simulation : integer := 0;
g_cpu_addr_width : integer := 19;
g_wishbone_addr_width : integer := 19
);
port(
sys_rst_n_i : in std_logic; -- global reset
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
cpu_clk_i : in std_logic; -- clock (not used now)
-- async chip select, active LOW
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_addr_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone master I/F
-------------------------------------------------------------------------------
-- wishbone clock input (refclk/2)
wb_clk_i : in std_logic;
-- wishbone master address output (m->s, common for all slaves)
wb_addr_o : out std_logic_vector(g_wishbone_addr_width - 1 downto 0);
-- wishbone master data output (m->s, common for all slaves)
wb_data_o : out std_logic_vector(31 downto 0);
-- wishbone cycle strobe (m->s, common for all slaves)
wb_stb_o : out std_logic;
-- wishbone write enable (m->s, common for all slaves)
wb_we_o : out std_logic;
-- wishbone byte select output (m->s, common for all slaves)
wb_sel_o : out std_logic_vector(3 downto 0);
-- wishbone cycle select (m->s, individual)
wb_cyc_o : out std_logic;
-- wishbone master data input (s->m, individual)
wb_data_i : in std_logic_vector(31 downto 0);
-- wishbone ACK input (s->m, individual)
wb_ack_i : in std_logic
);
end wb_cpu_bridge;
architecture behavioral of wb_cpu_bridge is
constant c_periph_addr_bits : integer := g_cpu_addr_width - g_wishbone_addr_width;
signal rw_sel, cycle_in_progress, cs_synced, rd_pulse, wr_pulse : std_logic;
signal cpu_data_reg : std_logic_vector(31 downto 0);
signal ack_muxed : std_logic;
signal data_in_muxed : std_logic_vector(31 downto 0);
signal long_cycle : std_logic;
signal wb_cyc_int : std_logic;
begin
gen_sync_chains_nosim : if(g_simulation = 0) generate
sync_ffs_cs : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map
(rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_cs_n_i,
synced_o => cs_synced,
npulse_o => open
);
sync_ffs_wr : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_wr_n_i,
synced_o => open,
npulse_o => wr_pulse
);
sync_ffs_rd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_rd_n_i,
synced_o => open,
npulse_o => rd_pulse
);
end generate gen_sync_chains_nosim;
gen_sim : if(g_simulation = 1) generate
wr_pulse <= not cpu_wr_n_i;
rd_pulse <= not cpu_rd_n_i;
cs_synced <= cpu_cs_n_i;
end generate gen_sim;
ack_muxed <= wb_ack_i;
data_in_muxed <= wb_data_i;
process(wb_clk_i)
begin
if(rising_edge(wb_clk_i)) then
if(sys_rst_n_i = '0') then
cpu_data_reg <= (others => '0');
cycle_in_progress <= '0';
rw_sel <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
wb_addr_o <= (others => '0');
wb_data_o <= (others => '0');
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
wb_cyc_int <= '0';
else
if(cs_synced = '0') then
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
if(cycle_in_progress = '1') then
if(ack_muxed = '1') then
if(rw_sel = '0') then
cpu_data_reg <= data_in_muxed;
end if;
cycle_in_progress <= '0';
wb_cyc_int <= '0';
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
else
cpu_nwait_o <= not long_cycle;
long_cycle <= '1';
end if;
elsif(rd_pulse = '1' or wr_pulse = '1') then
wb_we_o <= wr_pulse;
rw_sel <= wr_pulse;
wb_cyc_int <= '1';
wb_stb_o <= '1';
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
long_cycle <= '0';
-- periph_addr_reg <= cpu_addr_i (g_cpu_addr_width-1 downto g_wishbone_addr_width);
-- periph_sel_reg <= periph_sel;
if(wr_pulse = '1') then
wb_data_o <= cpu_data_b;
end if;
cycle_in_progress <= '1';
end if;
end if;
end if;
end if;
end process;
process(cpu_cs_n_i, cpu_rd_n_i, cpu_data_reg)
begin
if(cpu_cs_n_i = '0' and cpu_rd_n_i = '0') then
cpu_data_b <= cpu_data_reg;
else
cpu_data_b <= (others => 'Z');
end if;
end process;
wb_cyc_o <= wb_cyc_int;
end behavioral;
top/scb_test/wrsw_components_pkg.vhd 0 → 100644
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− 0
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library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wrsw_txtsu_pkg.all;
package wrsw_components_pkg is
component wb_cpu_bridge
generic (
g_simulation : integer := 0;
g_cpu_addr_width : integer := 19;
g_wishbone_addr_width : integer := 19);
port(
sys_rst_n_i : in std_logic; -- global reset
-- Atmel EBI bus
cpu_clk_i : in std_logic; -- clock (not used now)
-- async chip select, active LOW
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_addr_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-- Wishbone master I/F
-- wishbone clock input (refclk/2)
wb_clk_i : in std_logic;
-- wishbone master address output (m->s, common for all slaves)
wb_addr_o : out std_logic_vector(g_wishbone_addr_width - 1 downto 0);
-- wishbone master data output (m->s, common for all slaves)
wb_data_o : out std_logic_vector(31 downto 0);
-- wishbone cycle strobe (m->s, common for all slaves)
wb_stb_o : out std_logic;
-- wishbone write enable (m->s, common for all slaves)
wb_we_o : out std_logic;
-- wishbone byte select output (m->s, common for all slaves)
wb_sel_o : out std_logic_vector(3 downto 0);
-- wishbone cycle select (m->s, individual)
wb_cyc_o : out std_logic;
wb_data_i : in std_logic_vector(31 downto 0);
wb_ack_i : in std_logic
);
end component;
component wr_gtx_phy_virtex6
generic (
g_simulation : integer;
g_use_slave_tx_clock : integer);
port (
clk_ref_i : in std_logic;
tx_clk_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0');
end component;
component xwr_pps_gen
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic);
end component;
component xwrsw_tx_tsu
generic (
g_num_ports : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
timestamps_i : in t_txtsu_timestamp_array(g_num_ports-1 downto 0);
timestamps_ack_o : out std_logic_vector(g_num_ports -1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
component xwrsw_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
rtu_dst_port_mask_o : out std_logic_vector(31 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
rtu_drop_o : out std_logic;
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
rst_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
pps_p_o : out std_logic;
pps_raw_i : in std_logic;
sel_clk_sys_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
signal Control0 : std_logic_vector(35 downto 0);
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
end wrsw_components_pkg;
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