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Commit c70653b6 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update submodules

parent b2a62adf
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general-cores @ 12c045eb
Subproject commit ae5ff9aae00ed87718e925c4bfeb0b7b6792ad62
Subproject commit 12c045ebd49033d17f68b84cb6dec73a144f78cf
wr-cores @ 56a6681c
Subproject commit 86df7f9ccec063ab4f88baca1a53332f2e7d0571
Subproject commit 56a6681cb8dea06a18db2ed059672761361259bc
top/bare_top/scb_top_bare.vhd
+ 1
− 0
View file @ c70653b6
......@@ -634,6 +634,7 @@ begin
g_address_granularity => BYTE,
g_simulation => g_simulation,
g_tx_force_gap_length => 0,
g_tx_runt_padding => false,
g_pcs_16bit => true,
g_rx_buffer_size => 1024,
g_with_rx_buffer => true,
......
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