updates to pstats testbench

sim/pstats_gen.sv

@@ -17,7 +17,7 @@ module pstats_gen (rst_n_i, clk_i, trig_o);
     fork
     begin
       stop = 1'b1;
-      #21496us
+      #43496us
 //      #236us
       stop = 1'b0;
     end

sim/regs/pstats_regs.vh

+`define ADDR_PSTATS_CR                 6'h0
+`define PSTATS_CR_RD_EN_OFFSET 0
+`define PSTATS_CR_RD_EN 32'h00000001
+`define PSTATS_CR_RD_IRQ_OFFSET 1
+`define PSTATS_CR_RD_IRQ 32'h00000002
+`define PSTATS_CR_PORT_OFFSET 8
+`define PSTATS_CR_PORT 32'h00001f00
+`define PSTATS_CR_ADDR_OFFSET 16
+`define PSTATS_CR_ADDR 32'h001f0000
+`define ADDR_PSTATS_L1_CNT_VAL         6'h4
+`define ADDR_PSTATS_L2_CNT_VAL         6'h8
+`define ADDR_PSTATS_INFO               6'hc
+`define PSTATS_INFO_VER_OFFSET 0
+`define PSTATS_INFO_VER 32'h000000ff
+`define PSTATS_INFO_CPW_OFFSET 8
+`define PSTATS_INFO_CPW 32'h0000ff00
+`define PSTATS_INFO_CPP_OFFSET 16
+`define PSTATS_INFO_CPP 32'hffff0000
+`define ADDR_PSTATS_EIC_IDR            6'h20
+`define PSTATS_EIC_IDR_PORT0_OFFSET 0
+`define PSTATS_EIC_IDR_PORT0 32'h00000001
+`define PSTATS_EIC_IDR_PORT1_OFFSET 1
+`define PSTATS_EIC_IDR_PORT1 32'h00000002
+`define PSTATS_EIC_IDR_PORT2_OFFSET 2
+`define PSTATS_EIC_IDR_PORT2 32'h00000004
+`define PSTATS_EIC_IDR_PORT3_OFFSET 3
+`define PSTATS_EIC_IDR_PORT3 32'h00000008
+`define PSTATS_EIC_IDR_PORT4_OFFSET 4
+`define PSTATS_EIC_IDR_PORT4 32'h00000010
+`define PSTATS_EIC_IDR_PORT5_OFFSET 5
+`define PSTATS_EIC_IDR_PORT5 32'h00000020
+`define PSTATS_EIC_IDR_PORT6_OFFSET 6
+`define PSTATS_EIC_IDR_PORT6 32'h00000040
+`define PSTATS_EIC_IDR_PORT7_OFFSET 7
+`define PSTATS_EIC_IDR_PORT7 32'h00000080
+`define PSTATS_EIC_IDR_PORT8_OFFSET 8
+`define PSTATS_EIC_IDR_PORT8 32'h00000100
+`define PSTATS_EIC_IDR_PORT9_OFFSET 9
+`define PSTATS_EIC_IDR_PORT9 32'h00000200
+`define PSTATS_EIC_IDR_PORT10_OFFSET 10
+`define PSTATS_EIC_IDR_PORT10 32'h00000400
+`define PSTATS_EIC_IDR_PORT11_OFFSET 11
+`define PSTATS_EIC_IDR_PORT11 32'h00000800
+`define PSTATS_EIC_IDR_PORT12_OFFSET 12
+`define PSTATS_EIC_IDR_PORT12 32'h00001000
+`define PSTATS_EIC_IDR_PORT13_OFFSET 13
+`define PSTATS_EIC_IDR_PORT13 32'h00002000
+`define PSTATS_EIC_IDR_PORT14_OFFSET 14
+`define PSTATS_EIC_IDR_PORT14 32'h00004000
+`define PSTATS_EIC_IDR_PORT15_OFFSET 15
+`define PSTATS_EIC_IDR_PORT15 32'h00008000
+`define PSTATS_EIC_IDR_PORT16_OFFSET 16
+`define PSTATS_EIC_IDR_PORT16 32'h00010000
+`define PSTATS_EIC_IDR_PORT17_OFFSET 17
+`define PSTATS_EIC_IDR_PORT17 32'h00020000
+`define ADDR_PSTATS_EIC_IER            6'h24
+`define PSTATS_EIC_IER_PORT0_OFFSET 0
+`define PSTATS_EIC_IER_PORT0 32'h00000001
+`define PSTATS_EIC_IER_PORT1_OFFSET 1
+`define PSTATS_EIC_IER_PORT1 32'h00000002
+`define PSTATS_EIC_IER_PORT2_OFFSET 2
+`define PSTATS_EIC_IER_PORT2 32'h00000004
+`define PSTATS_EIC_IER_PORT3_OFFSET 3
+`define PSTATS_EIC_IER_PORT3 32'h00000008
+`define PSTATS_EIC_IER_PORT4_OFFSET 4
+`define PSTATS_EIC_IER_PORT4 32'h00000010
+`define PSTATS_EIC_IER_PORT5_OFFSET 5
+`define PSTATS_EIC_IER_PORT5 32'h00000020
+`define PSTATS_EIC_IER_PORT6_OFFSET 6
+`define PSTATS_EIC_IER_PORT6 32'h00000040
+`define PSTATS_EIC_IER_PORT7_OFFSET 7
+`define PSTATS_EIC_IER_PORT7 32'h00000080
+`define PSTATS_EIC_IER_PORT8_OFFSET 8
+`define PSTATS_EIC_IER_PORT8 32'h00000100
+`define PSTATS_EIC_IER_PORT9_OFFSET 9
+`define PSTATS_EIC_IER_PORT9 32'h00000200
+`define PSTATS_EIC_IER_PORT10_OFFSET 10
+`define PSTATS_EIC_IER_PORT10 32'h00000400
+`define PSTATS_EIC_IER_PORT11_OFFSET 11
+`define PSTATS_EIC_IER_PORT11 32'h00000800
+`define PSTATS_EIC_IER_PORT12_OFFSET 12
+`define PSTATS_EIC_IER_PORT12 32'h00001000
+`define PSTATS_EIC_IER_PORT13_OFFSET 13
+`define PSTATS_EIC_IER_PORT13 32'h00002000
+`define PSTATS_EIC_IER_PORT14_OFFSET 14
+`define PSTATS_EIC_IER_PORT14 32'h00004000
+`define PSTATS_EIC_IER_PORT15_OFFSET 15
+`define PSTATS_EIC_IER_PORT15 32'h00008000
+`define PSTATS_EIC_IER_PORT16_OFFSET 16
+`define PSTATS_EIC_IER_PORT16 32'h00010000
+`define PSTATS_EIC_IER_PORT17_OFFSET 17
+`define PSTATS_EIC_IER_PORT17 32'h00020000
+`define ADDR_PSTATS_EIC_IMR            6'h28
+`define PSTATS_EIC_IMR_PORT0_OFFSET 0
+`define PSTATS_EIC_IMR_PORT0 32'h00000001
+`define PSTATS_EIC_IMR_PORT1_OFFSET 1
+`define PSTATS_EIC_IMR_PORT1 32'h00000002
+`define PSTATS_EIC_IMR_PORT2_OFFSET 2
+`define PSTATS_EIC_IMR_PORT2 32'h00000004
+`define PSTATS_EIC_IMR_PORT3_OFFSET 3
+`define PSTATS_EIC_IMR_PORT3 32'h00000008
+`define PSTATS_EIC_IMR_PORT4_OFFSET 4
+`define PSTATS_EIC_IMR_PORT4 32'h00000010
+`define PSTATS_EIC_IMR_PORT5_OFFSET 5
+`define PSTATS_EIC_IMR_PORT5 32'h00000020
+`define PSTATS_EIC_IMR_PORT6_OFFSET 6
+`define PSTATS_EIC_IMR_PORT6 32'h00000040
+`define PSTATS_EIC_IMR_PORT7_OFFSET 7
+`define PSTATS_EIC_IMR_PORT7 32'h00000080
+`define PSTATS_EIC_IMR_PORT8_OFFSET 8
+`define PSTATS_EIC_IMR_PORT8 32'h00000100
+`define PSTATS_EIC_IMR_PORT9_OFFSET 9
+`define PSTATS_EIC_IMR_PORT9 32'h00000200
+`define PSTATS_EIC_IMR_PORT10_OFFSET 10
+`define PSTATS_EIC_IMR_PORT10 32'h00000400
+`define PSTATS_EIC_IMR_PORT11_OFFSET 11
+`define PSTATS_EIC_IMR_PORT11 32'h00000800
+`define PSTATS_EIC_IMR_PORT12_OFFSET 12
+`define PSTATS_EIC_IMR_PORT12 32'h00001000
+`define PSTATS_EIC_IMR_PORT13_OFFSET 13
+`define PSTATS_EIC_IMR_PORT13 32'h00002000
+`define PSTATS_EIC_IMR_PORT14_OFFSET 14
+`define PSTATS_EIC_IMR_PORT14 32'h00004000
+`define PSTATS_EIC_IMR_PORT15_OFFSET 15
+`define PSTATS_EIC_IMR_PORT15 32'h00008000
+`define PSTATS_EIC_IMR_PORT16_OFFSET 16
+`define PSTATS_EIC_IMR_PORT16 32'h00010000
+`define PSTATS_EIC_IMR_PORT17_OFFSET 17
+`define PSTATS_EIC_IMR_PORT17 32'h00020000
+`define ADDR_PSTATS_EIC_ISR            6'h2c
+`define PSTATS_EIC_ISR_PORT0_OFFSET 0
+`define PSTATS_EIC_ISR_PORT0 32'h00000001
+`define PSTATS_EIC_ISR_PORT1_OFFSET 1
+`define PSTATS_EIC_ISR_PORT1 32'h00000002
+`define PSTATS_EIC_ISR_PORT2_OFFSET 2
+`define PSTATS_EIC_ISR_PORT2 32'h00000004
+`define PSTATS_EIC_ISR_PORT3_OFFSET 3
+`define PSTATS_EIC_ISR_PORT3 32'h00000008
+`define PSTATS_EIC_ISR_PORT4_OFFSET 4
+`define PSTATS_EIC_ISR_PORT4 32'h00000010
+`define PSTATS_EIC_ISR_PORT5_OFFSET 5
+`define PSTATS_EIC_ISR_PORT5 32'h00000020
+`define PSTATS_EIC_ISR_PORT6_OFFSET 6
+`define PSTATS_EIC_ISR_PORT6 32'h00000040
+`define PSTATS_EIC_ISR_PORT7_OFFSET 7
+`define PSTATS_EIC_ISR_PORT7 32'h00000080
+`define PSTATS_EIC_ISR_PORT8_OFFSET 8
+`define PSTATS_EIC_ISR_PORT8 32'h00000100
+`define PSTATS_EIC_ISR_PORT9_OFFSET 9
+`define PSTATS_EIC_ISR_PORT9 32'h00000200
+`define PSTATS_EIC_ISR_PORT10_OFFSET 10
+`define PSTATS_EIC_ISR_PORT10 32'h00000400
+`define PSTATS_EIC_ISR_PORT11_OFFSET 11
+`define PSTATS_EIC_ISR_PORT11 32'h00000800
+`define PSTATS_EIC_ISR_PORT12_OFFSET 12
+`define PSTATS_EIC_ISR_PORT12 32'h00001000
+`define PSTATS_EIC_ISR_PORT13_OFFSET 13
+`define PSTATS_EIC_ISR_PORT13 32'h00002000
+`define PSTATS_EIC_ISR_PORT14_OFFSET 14
+`define PSTATS_EIC_ISR_PORT14 32'h00004000
+`define PSTATS_EIC_ISR_PORT15_OFFSET 15
+`define PSTATS_EIC_ISR_PORT15 32'h00008000
+`define PSTATS_EIC_ISR_PORT16_OFFSET 16
+`define PSTATS_EIC_ISR_PORT16 32'h00010000
+`define PSTATS_EIC_ISR_PORT17_OFFSET 17
+`define PSTATS_EIC_ISR_PORT17 32'h00020000

testbench/wrsw_pstats/main.sv

 `include "pstats_gen.sv"
 `include "if_wb_master.svh"
 
-`define TRIG_WIDTH 17
+`define TRIG_WIDTH 38
 `define NPORTS 8
 
 module main;
@@ -93,6 +93,11 @@ module main;
 
           acc.write('h0, 'h000002);
           acc.read('h4, dat);
+          acc.read('h8, dat);
+          acc.write('h0, 'h000001);
+          acc.read('h4, dat);
+          acc.read('h8, dat);
+
           acc.write('h2c, 'h01);
           acc.write('h0, 'h000102);
           acc.read('h4, dat);
@@ -150,6 +155,7 @@ module main;
         //  acc.write('h0, 'h040001);
         //  acc.read('h4, dat);
         //end
+
       //end 
 
       //#500ns

testbench/wrsw_pstats/run.do

@@ -5,6 +5,6 @@ set StdArithNoWarnings 1
 set NumericStdNoWarnings 1
 do wave.do
 radix -hexadecimal
-run 21500us
+run 43500us
 wave zoomfull
 radix -hexadecimal

testbench/wrsw_pstats/wave.do

 onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /main/rst_n
-add wave -noupdate /main/DUT/nrst_cntrs
 add wave -noupdate /main/clk_sys
 add wave -noupdate /main/DUT/g_keep_ov
 add wave -noupdate /main/TRIG_GEN/trig_o
-add wave -noupdate -divider
+add wave -noupdate -divider <NULL>
 add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_adr_d1
 add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ov_cnt_o
-
 add wave -noupdate -divider <NULL>
 add wave -noupdate -divider <NULL>
 add wave -noupdate /main/DUT/L2_events
 add wave -noupdate /main/DUT/L3_events
-
-add wave -noupdate -divider <NULL>
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/dbg_evt_ov_o
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/dbg_cnt_ov_o
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/cnt_ov
-add wave  -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ov_cnt_o
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_i
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_reg
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_clr
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_sub
-add wave -noupdate -height 16 /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/cnt_state
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_adr
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_wr
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_dat_in
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/mem_dat_out
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/events_grant
-add wave -noupdate -expand /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/RAM_A1/gen_single_clk/U_RAM_SC/ram
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ext_adr_i
-add wave -noupdate /main/DUT/GEN_PCNT(0)/PER_PORT_CNT/ext_dat_o
-
 add wave -noupdate -divider <NULL>
-add wave -noupdate /main/DUT/L2_CNT/dbg_evt_ov_o
-add wave -noupdate /main/DUT/L2_CNT/dbg_cnt_ov_o
-add wave -noupdate /main/DUT/L2_CNT/events_reg
-add wave -noupdate /main/DUT/L2_CNT/events_clr
-add wave -noupdate /main/DUT/L2_CNT/events_sub
-add wave -noupdate /main/DUT/L2_CNT/cnt_state
-add wave -noupdate /main/DUT/L2_CNT/mem_adr
-add wave -noupdate /main/DUT/L2_CNT/mem_wr
-add wave -noupdate /main/DUT/L2_CNT/mem_dat_in
-add wave -noupdate /main/DUT/L2_CNT/mem_dat_out
-add wave -noupdate -expand /main/DUT/L2_CNT/RAM_A1/gen_single_clk/U_RAM_SC/ram
-add wave -noupdate /main/DUT/L2_CNT/ext_adr_i
-add wave -noupdate /main/DUT/L2_CNT/ext_dat_o
-
-add wave -noupdate -divider
 add wave -noupdate /main/DUT/irq
-add wave -noupdate /main/DUT/CNTRS_IRQ/cnt_state
-
+add wave -noupdate -height 16 /main/DUT/CNTRS_IRQ/cnt_state
 add wave -noupdate /main/DUT/CNTRS_IRQ/irq_i
 add wave -noupdate /main/DUT/CNTRS_IRQ/events_reg
 add wave -noupdate /main/DUT/CNTRS_IRQ/events_clr
@@ -66,7 +28,6 @@ add wave -noupdate /main/DUT/IRQ_adr
 add wave -noupdate /main/DUT/IRQ_we
 add wave -noupdate /main/DUT/IRQ_dat_out
 add wave -noupdate /main/DUT/wb_int_o
-
 add wave -noupdate -divider <NULL>
 add wave -noupdate -divider <NULL>
 add wave -noupdate /main/DUT/wb_adr_i
@@ -78,15 +39,22 @@ add wave -noupdate /main/DUT/wb_stall_o
 add wave -noupdate -height 16 /main/DUT/rd_state
 add wave -noupdate /main/DUT/wb_regs_out.cr_rd_en_o
 add wave -noupdate /main/DUT/wb_regs_out.cr_rd_en_load_o
+add wave -noupdate /main/DUT/wb_regs_out.cr_rd_irq_o
+add wave -noupdate /main/DUT/wb_regs_out.cr_rd_irq_load_o
 add wave -noupdate /main/DUT/wb_regs_out.cr_port_o
 add wave -noupdate /main/DUT/wb_regs_out.cr_addr_o
 add wave -noupdate /main/DUT/wb_regs_in.cr_rd_en_i
-add wave -noupdate /main/DUT/wb_regs_in.L1_cnt_val_i
+add wave -noupdate /main/DUT/wb_regs_in.l1_cnt_val_i
+add wave -noupdate /main/DUT/IRQ_adr
+add wave -noupdate /main/DUT/IRQ_dat_out
+add wave -noupdate /main/DUT/L2_rd_val
+add wave -noupdate /main/DUT/rd_val
+add wave -noupdate /main/DUT/rd_irq
+add wave -noupdate /main/DUT/wb_regs_in.l2_cnt_val_i
 add wave -noupdate -divider <NULL>
-add wave -noupdate /main/DUMMY/regs
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
-configure wave -namecolwidth 150
+WaveRestoreCursors {{Cursor 1} {21003165000000 fs} 0}
+configure wave -namecolwidth 293
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
 configure wave -signalnamewidth 1
@@ -100,4 +68,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 fs} {111300 ns}
+WaveRestoreZoom {0 fs} {22575 us}