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Commit a5a71704 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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scb_18ports: relaxing dmtd clock maxskew constraint

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top/scb_18ports/scb_top_synthesis.vhd
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......@@ -234,7 +234,7 @@ architecture Behavioral of scb_top_synthesis is
signal pllout_clk_fb : std_logic;
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "0.5ns";
attribute maxskew of clk_dmtd : signal is "1.0ns";
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
......
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