swcore[mpm new]: input block passes less basic tests

modules/wrsw_swcore/xswc_input_block.vhd

@@ -872,7 +872,6 @@ architecture syn of xswc_input_block is
             
             if(tp_stuck = '0' ) then  -- un-stuck the input :)
 
-              mmu_force_free_req <= '1';
               s_rcv_pck          <= S_IDLE;
           
             else -- still stuck
@@ -1620,6 +1619,17 @@ architecture syn of xswc_input_block is
           --===========================================================================================
             if(ll_wr_req = '1' and ll_wr_done_i = '1') then -- written
               ll_wr_req                <= '0';
+              ll_entry.valid           <= '0';
+              ll_entry.eof             <= '0';
+              ll_entry.addr            <= (others => '0');
+              ll_entry.dsel            <= (others => '0');
+              ll_entry.size            <= (others => '0');             
+              ll_entry.next_page       <= (others => '0');
+              ll_entry.next_page_valid <= '0';                            
+              ll_entry.oob_size        <= (others => '0');
+              ll_entry.oob_dsel        <= (others => '0');    
+              ll_entry.first_page_clr  <= '0';   
+
               if(ll_entry.first_page_clr = '1') then
                 if(pckinter_page_in_advance = '1' and pckstart_page_in_advance = '1') then
                   s_ll_write               <= S_READY_FOR_PGR_AND_DLAST;  

testbench/scb_top/main.sv

@@ -209,14 +209,15 @@ module main;
       rtu.set_port_config(4, 1, 1, 1);
       rtu.set_port_config(3, 1, 1, 1);
       rtu.set_port_config(5, 1, 1, 1);
-      //rtu.add_static_rule('{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1'h1);
-      rtu.add_static_rule('{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<0);
-      rtu.add_static_rule('{'h01, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<1);
-      rtu.add_static_rule('{'h02, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<2);
-      rtu.add_static_rule('{'h03, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<3);
-      rtu.add_static_rule('{'h04, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<4);
-      rtu.add_static_rule('{'h05, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<5);
-      rtu.add_static_rule('{'h06, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1<<6);
+      rtu.set_port_config(6, 1, 1, 1);
+//      rtu.add_static_rule('{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 1'h1);
+       rtu.add_static_rule('{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<0));
+       rtu.add_static_rule('{'h01, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<1));
+       rtu.add_static_rule('{'h02, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<2));
+       rtu.add_static_rule('{'h03, 'h50, 'hca, 'hfe, 'hba, 'hbe}, 8'h0); //dump
+       rtu.add_static_rule('{'h04, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<4));
+       rtu.add_static_rule('{'h05, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<5));
+       rtu.add_static_rule('{'h06, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<6));
       
      // rtu.set_hash_poly();
       
@@ -233,13 +234,13 @@ module main;
 
       fork
          
-          begin 
-             for(int i=0;i<20;i++)
-               begin
-                  $display("Try f_1:%d", i);
-                  tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[6].send /* src */, ports[0].recv /* sink */, 6 /* srcPort */ , 0 /* dstPort */);
-               end
-         end
+//            begin 
+//              for(int i=0;i<20;i++)
+//                 begin
+//                    $display("Try f_1:%d", i);
+//                    tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[6].send /* src */, ports[0].recv /* sink */, 6 /* srcPort */ , 0 /* dstPort */);
+//                 end
+//           end
           begin 
              for(int g=0;g<20;g++)
                begin
@@ -258,32 +259,32 @@ module main;
              for(int g=0;g<20;g++)
                begin
                   $display("Try f_4:%d", g);
-                  tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[3].send /* src */, ports[3].recv /* sink */,  3 /* srcPort */ , 3 /* dstPort */);
-               end
-          end       
-          begin 
-             for(int g=0;g<20;g++)
-               begin
-                  $display("Try f_4:%d", g);
-                  tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[2].send /* src */, ports[4].recv /* sink */,  2 /* srcPort */ , 4 /* dstPort */);
-               end
-          end       
-
-          begin 
-             for(int g=0;g<20;g++)
-               begin
-                  $display("Try f_4:%d", g);
-                  tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[1].send /* src */, ports[5].recv /* sink */,  1 /* srcPort */ , 5 /* dstPort */);
-               end
-          end       
-
-          begin 
-             for(int g=0;g<20;g++)
-               begin
-                  $display("Try f_4:%d", g);
-                  tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[0].send /* src */, ports[6].recv /* sink */,  0 /* srcPort */ , 6 /* dstPort */);
+                 tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[3].send /* src */, ports[3].recv /* sink */,  3 /* srcPort */ , 3 /* dstPort */);
                end
           end       
+           begin 
+              for(int g=0;g<20;g++)
+                begin
+                   $display("Try f_4:%d", g);
+                   tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[2].send /* src */, ports[4].recv /* sink */,  2 /* srcPort */ , 4 /* dstPort */);
+                end
+           end       
+ 
+           begin 
+              for(int g=0;g<20;g++)
+                begin
+                   $display("Try f_5:%d", g);
+                   tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[1].send /* src */, ports[5].recv /* sink */,  1 /* srcPort */ , 5 /* dstPort */);
+                end
+           end       
+ 
+//            begin 
+//               for(int g=0;g<20;g++)
+//                 begin
+//                    $display("Try f_6:%d", g);
+//                    tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[0].send /* src */, ports[6].recv /* sink */,  0 /* srcPort */ , 6 /* dstPort */);
+//                 end
+//            end       
 
          forever begin
             nic.update(DUT.U_Top.U_Wrapped_SCBCore.vic_irqs[0]);

testbench/swcore/Manifest.py

@@ -18,7 +18,7 @@ vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/si
 modules = {"local":
 		[ 
 		  "../../ip_cores/wr-cores",
-		  "../../ip_cores/general-cores/modules/genrams/",
+		  "../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/",
 		  "../../modules/wrsw_swcore",
 		],
 	    #"git" :