feed softpll with locked signals from plls multiplying ext. 10MHz in to 62.5MHz
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- ip_cores/wr-cores 1 addition, 1 deletionip_cores/wr-cores
- modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd 3 additions, 0 deletionsmodules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
- platform/xilinx/ext_pll_100_to_62m.vhd 5 additions, 4 deletionsplatform/xilinx/ext_pll_100_to_62m.vhd
- platform/xilinx/ext_pll_10_to_100.vhd 5 additions, 4 deletionsplatform/xilinx/ext_pll_10_to_100.vhd
- top/bare_top/scb_top_bare.vhd 2 additions, 0 deletionstop/bare_top/scb_top_bare.vhd
- top/bare_top/wrsw_components_pkg.vhd 2 additions, 0 deletionstop/bare_top/wrsw_components_pkg.vhd
- top/bare_top/wrsw_top_pkg.vhd 1 addition, 0 deletionstop/bare_top/wrsw_top_pkg.vhd
- top/scb_18ports/scb_top_synthesis.vhd 17 additions, 7 deletionstop/scb_18ports/scb_top_synthesis.vhd
- top/scb_8ports/scb_top_synthesis.vhd 16 additions, 7 deletionstop/scb_8ports/scb_top_synthesis.vhd
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