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White Rabbit Switch - Gateware
Commits
647e53f4
Commit
647e53f4
authored
11 years ago
by
Maciej Lipinski
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[RTU]: rtu_port_new: adding handling of exceptional situations in FSM
parent
d4176637
Branches
v3.3-dev
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modules/wrsw_rtu/rtu_port_new.vhd
+10
-5
10 additions, 5 deletions
modules/wrsw_rtu/rtu_port_new.vhd
with
10 additions
and
5 deletions
modules/wrsw_rtu/rtu_port_new.vhd
+
10
−
5
View file @
647e53f4
...
...
@@ -84,7 +84,7 @@ entity rtu_port_new is
-- 1 indicates that coresponding RTU port is idle and ready to accept requests
rtu_idle_o
:
out
std_logic
;
rtu_rq_i
:
in
t_rtu_request
;
rtu_rq_aboard_i
:
in
std_logic
;
rtu_rq_aboard_i
:
in
std_logic
;
-- not used yet
rtu_rsp_o
:
out
t_rtu_response
;
rtu_rsp_ack_i
:
in
std_logic
;
...
...
@@ -319,7 +319,7 @@ begin
-- request to aboard full match
full_match_aboard
<=
(
not
full_match_valid
)
and
-- suppress when we have replay from full match
((
aboard_possible
and
fast_match_wr_req
)
or
-- new request when full match busy
(
rtu_rq_aboard_i
));
-- other externa, e.g. from swcore
(
rtu_rq_aboard_i
));
-- other externa, e.g. from swcore
, **not implemented yet
--------------------------------------------------------------------------------------------
-- register input request to make it available for both matches (full/fast)
--------------------------------------------------------------------------------------------
...
...
@@ -460,7 +460,6 @@ begin
------------------------------------------------------------------------------------------------------------
port_state
<=
S_IDLE
;
rsp
<=
c_rtu_rsp_zero
;
-- fast_match <= c_match_zero;
delayed_full_match_wr_req
<=
'0'
;
------------------------------------------------------------------------------------------------------------
else
...
...
@@ -503,7 +502,10 @@ begin
end
if
;
end
if
;
elsif
(
rtu_rq_aboard_i
=
'1'
and
fast_match
.
valid
=
'0'
)
then
-- TODO: this should not happen -> handle exeption
-- TODO: this should not happen -> handle exeption
port_state
<=
S_FINAL_MASK
;
rsp
<=
c_rtu_rsp_drop
;
delayed_full_match_wr_req
<=
'0'
;
end
if
;
------------------------------------------------------------------------------------------------------------
...
...
@@ -605,7 +607,10 @@ begin
------------------------------------------------------------------------------------------------------------
--| OTHER:
------------------------------------------------------------------------------------------------------------
when
others
=>
null
;
when
others
=>
port_state
<=
S_IDLE
;
rsp
<=
c_rtu_rsp_zero
;
delayed_full_match_wr_req
<=
'0'
;
------------------------------------------------------------------------------------------------------------
end
case
;
if
(
rtu_rsp_ack_i
=
'1'
and
rsp
.
valid
=
'1'
)
then
...
...
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