re-organized top modules to have separate GTX-less simulation top core
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- syn/scb_18ports/Manifest.py 12 additions, 0 deletionssyn/scb_18ports/Manifest.py
- syn/scb_18ports/test_scb.xise 1352 additions, 0 deletionssyn/scb_18ports/test_scb.xise
- top/bare_top/Manifest.py 7 additions, 0 deletionstop/bare_top/Manifest.py
- top/bare_top/scb_top_bare.vhd 597 additions, 0 deletionstop/bare_top/scb_top_bare.vhd
- top/bare_top/scb_top_sim.vhd 184 additions, 0 deletionstop/bare_top/scb_top_sim.vhd
- top/bare_top/wb_cpu_bridge.vhd 0 additions, 0 deletionstop/bare_top/wb_cpu_bridge.vhd
- top/bare_top/wrsw_components_pkg.vhd 44 additions, 2 deletionstop/bare_top/wrsw_components_pkg.vhd
- top/bare_top/wrsw_top_pkg.vhd 281 additions, 0 deletionstop/bare_top/wrsw_top_pkg.vhd
- top/scb_18ports/Manifest.py 7 additions, 0 deletionstop/scb_18ports/Manifest.py
- top/scb_18ports/scb_top_synthesis.ucf 212 additions, 0 deletionstop/scb_18ports/scb_top_synthesis.ucf
- top/scb_18ports/scb_top_synthesis.vhd 500 additions, 0 deletionstop/scb_18ports/scb_top_synthesis.vhd
- top/scb_6ports/Manifest.py 2 additions, 2 deletionstop/scb_6ports/Manifest.py
- top/scb_6ports/scb_top_synthesis.ucf 45 additions, 4 deletionstop/scb_6ports/scb_top_synthesis.ucf
- top/scb_6ports/scb_top_synthesis.vhd 450 additions, 0 deletionstop/scb_6ports/scb_top_synthesis.vhd
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