TOP+RTU:connected RTU events to PSTAT, and some modifications in RTU regarding events

modules/wrsw_rtu/xwrsw_rtu_new.vhd

@@ -784,15 +784,20 @@ begin
             vlan_tab_rd_entry4fast_match.prio,
             vlan_tab_rd_entry4fast_match.has_prio);
 
-  rmon_events_gen: for i in 0 to (g_num_ports - 1) generate
-    rmon_events_o((i+1)*g_rmon_events_bits_pp-1 downto i*g_rmon_events_bits_pp) <= 
-       std_logic(req_i(i).valid                                    ) & -- valid request 
-       std_logic(rsp(i).valid and rsp_ack_i(i)                     ) & -- valid respons
-       std_logic(rsp(i).valid and rsp_ack_i(i) and rsp(i).drop     ) & -- dropped
-       std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.hp) & -- FastMatch: high priority frames
-       std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.ff) & -- FastMatch: fast forward (as config)                   
-       std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.nf) & -- FastMatch: non-forward (as config)
-       "00";                                                           -- spare, to make the number nice ;-P  
-  end generate rmon_events_gen;
-
+  events_gen: if(g_rmon_events_bits_pp = 8 ) generate
+    rmon_events_gen: for i in 0 to (g_num_ports - 1) generate
+      rmon_events_o((i+1)*g_rmon_events_bits_pp-1 downto i*g_rmon_events_bits_pp) <= 
+        std_logic(req_i(i).valid                                    ) & -- valid request 
+        std_logic(rsp(i).valid and rsp_ack_i(i)                     ) & -- valid respons
+        std_logic(rsp(i).valid and rsp_ack_i(i) and rsp(i).drop     ) & -- dropped
+        std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.hp) & -- FastMatch: high priority frames
+        std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.ff) & -- FastMatch: fast forward (as config)                   
+        std_logic(fast_match_rsp_valid(i) and fast_match_rsp_data.nf) & -- FastMatch: non-forward (as config)
+        "00";                                                  -- spare, to make the number nice ;-P  
+    end generate rmon_events_gen;
+  end generate events_gen;
+  no_events_gen: if(g_rmon_events_bits_pp /= 8 ) generate
+    rmon_events_o <= (others=>'0'); 
+    assert true report "g_rmon_events_bits_pp not equal to the defined number of RMON event ";
+  end generate no_events_gen;
 end behavioral;

modules/wrsw_swcore/swc_alloc_resource_manager.vhd

@@ -290,6 +290,7 @@ begin
   end generate GEN_DEBUG;
   GEN_NO_DEBUG: if ((g_total_num_pages_width*g_resource_num) > g_num_dbg_vector_width) generate
       dbg_o <= (others =>'0');
+      assert true report "g_num_dbg_vector_width to small for the defined number debug bits";
   end generate GEN_NO_DEBUG;
 
  

top/bare_top/scb_top_bare.vhd

@@ -134,9 +134,9 @@ architecture rtl of scb_top_bare is
   constant c_NUM_PORTS     : integer := g_num_ports;
   constant c_MAX_PORTS     : integer := 18;
   constant c_NUM_GL_PAUSE  : integer := 2; -- number of output global PAUSE sources for SWcore
-  constant c_RMON_RTU_PP   : integer := 8; -- number of RMON events per port
+  constant c_RTU_EVENTS    : integer := 8; -- number of RMON events per port
   constant c_DBG_V_SWCORE  : integer := (3*10); -- 3 resources, each has with of CNT of 10 bits
-  
+  constant c_ALL_EVENTS    : integer := c_RTU_EVENTS + c_epevents_sz;
 --   constant c_epevents_sz   : integer := 15;
 -------------------------------------------------------------------------------
 -- Interconnect & memory layout
@@ -264,7 +264,10 @@ architecture rtl of scb_top_bare is
   signal dummy                : std_logic_vector(31 downto 0);
   signal tru_enabled          : std_logic;
 
-  signal rmon_events : std_logic_vector(c_NUM_PORTS*c_epevents_sz-1 downto 0);  --15 is no. of cntrs per port
+  -- PSTAT: RMON counters
+  signal rtu_events  : std_logic_vector(c_NUM_PORTS*c_RTU_EVENTS  -1 downto 0);  --
+  signal ep_events   : std_logic_vector(c_NUM_PORTS*c_epevents_sz -1 downto 0);  --
+  signal rmon_events : std_logic_vector(c_NUM_PORTS*c_ALL_EVENTS  -1 downto 0);  --
 
   --TEMP
   signal dummy_events : std_logic_vector(c_NUM_PORTS*2-1 downto 0);
@@ -608,7 +611,7 @@ begin
           fc_rx_pause_prio_mask_o => fc_rx_pause(i).classes,    
           ----------------------------
 
-          rmon_events_o => rmon_events((i+1)*c_epevents_sz-1 downto i*c_epevents_sz),
+          rmon_events_o => ep_events((i+1)*c_epevents_sz-1 downto i*c_epevents_sz),
 
           led_link_o => led_link_o(i),
           led_act_o  => led_act_o(i));
@@ -724,7 +727,7 @@ begin
         g_cpu_port_num                    => g_num_ports, -- g_num_ports-nt port is connected to CPU
         g_port_mask_bits                  => g_num_ports+1,
         g_handle_only_single_req_per_port => true,
-        g_rmon_events_bits_pp             => c_RMON_RTU_PP)
+        g_rmon_events_bits_pp             => c_RTU_EVENTS)
       port map (
         clk_sys_i  => clk_sys,
         rst_n_i    => rst_n_sys,--rst_n_periph,
@@ -738,7 +741,7 @@ begin
         rtu2tru_o  => rtu2tru,
         tru_enabled_i => tru_enabled,
         -------------------------------
-        rmon_events_o => open,
+        rmon_events_o => rtu_events,
         wb_i       => cnx_master_out(c_SLAVE_RTU),
         wb_o       => cnx_master_in(c_SLAVE_RTU));
 
@@ -912,7 +915,7 @@ begin
       g_interface_mode      => PIPELINED,
       g_address_granularity => BYTE,
       g_nports => c_NUM_PORTS,
-      g_cnt_pp => c_epevents_sz,
+      g_cnt_pp => c_ALL_EVENTS,
       g_cnt_pw => 4)
     port map(
       rst_n_i => rst_n_periph,
@@ -922,7 +925,12 @@ begin
   
       wb_i  => cnx_master_out(c_SLAVE_PSTATS),
       wb_o  => cnx_master_in(c_SLAVE_PSTATS));
-
+ 
+  gen_events_assemble : for i in 0 to c_NUM_PORTS-1 generate
+    rmon_events((i+1)*c_ALL_EVENTS-1 downto i*c_ALL_EVENTS) <= 
+                rtu_events((i+1)*c_RTU_EVENTS-1 downto i*c_RTU_EVENTS) &
+                ep_events ((i+1)*c_epevents_sz-1 downto i*c_epevents_sz);
+  end generate gen_events_assemble;
 
   --TEMP
   U_DUMMY: dummy_rmon