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f440fba2
Commit
f440fba2
authored
Jul 23, 2014
by
Grzegorz Daniluk
Committed by
Miguel Jimenez Lopez
Sep 04, 2019
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softpll: update header file to follow latest changes in ext SPLL
parent
7e8070eb
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2 changed files
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263 additions
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199 deletions
+263
-199
softpll-regs.h
kernel/wbgen-regs/softpll-regs.h
+113
-91
softpll-regs.wb
kernel/wbgen-regs/softpll-regs.wb
+150
-108
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kernel/wbgen-regs/softpll-regs.h
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f440fba2
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kernel/wbgen-regs/softpll-regs.wb
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f440fba2
...
...
@@ -9,16 +9,15 @@ peripheral {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = CONSTANT;
value = 0;
};
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
...
...
@@ -41,11 +40,11 @@ peripheral {
};
field {
name = "
Enable Period Measurement
";
prefix = "
PER_EN
";
name = "
Debug queue supported
";
prefix = "
DBG_SUPPORTED
";
type = BIT;
access_bus = READ_
WRITE
;
access_dev =
READ
_ONLY;
access_bus = READ_
ONLY
;
access_dev =
WRITE
_ONLY;
};
};
...
...
@@ -55,17 +54,15 @@ peripheral {
reg {
name = "External Clock Control Register";
prefix = "ECCR";
prefix = "ECCR";
field {
name = "Enable External Clock
BB Detector
";
field {
name = "Enable External Clock
PLL
";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
...
...
@@ -76,28 +73,6 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
...
...
@@ -107,73 +82,98 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
reg {
name = "Aligner Control Register";
prefix = "AL_CR";
field {
name = "DMTD Clock Undersampling Divider
";
prefix = "GATE_DIV
";
size = 6
;
type = SLV
;
field {
name = "Aligner sample valid/select on channel
";
prefix = "VALID
";
type = SLV
;
size = 9
;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
name = "Aligner Counter REF register";
prefix = "AL_CREF";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "
Output Channel Control Register
";
prefix = "
OCCR
";
name = "
DMTD VCO Frequency
";
prefix = "
F_DMTD
";
field {
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 8;
size =
2
8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "R
eference Channel Enable Register
";
prefix = "
RCER
";
name = "R
EF VCO Frequency
";
prefix = "
F_REF
";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
...
...
@@ -181,47 +181,87 @@ peripheral {
};
reg {
name = "
Output Channel Enable Register
";
prefix = "
OCER
";
name = "
EXT VCO Frequency
";
prefix = "
F_EXT
";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 8;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
field {
name = "Period error value";
prefix = "ERROR";
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
type = SLV;
size =
16
;
size =
8
;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid
";
prefix = "VALID
";
type = BIT
;
access_bus = READ_ONLY
;
access_
dev = WRITE_ONLY
;
}
;
name = "Output Channel locked flag
";
prefix = "OUT_LOCK
";
type = SLV
;
size = 8
;
access_
bus = READ_WRITE
;
access_dev = READ_ONLY
;
};
};
reg {
reg {
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
align = 8;
name = "Helper DAC Output";
prefix = "DAC_HPLL";
...
...
@@ -253,7 +293,7 @@ peripheral {
};
reg {
name = "Deglitcher threshold";
name = "D
DMTD D
eglitcher threshold";
prefix = "DEGLITCH_THR";
field {
...
...
@@ -284,12 +324,15 @@ peripheral {
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
optional = "g_with_debug_fifo";
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
...
...
@@ -340,7 +383,6 @@ peripheral {
};
irq {
name = "Got a tag";
prefix = "TAG";
...
...
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