The White Rabbit Network Interface Card (WR-NIC) project implements a
NIC with White Rabbit (WR) synchronization features that can be plugged
in a PCIe slot of a conventional computer with Linux OS. It facilitates
the communication between software applications that runs in the host
computer and the WR network providing a standard interface.
Figure: WR-NIC block diagram with all the gateware components
The Digital Input Output (DIO) core allows configuration of each one
of the 5 channels of the DIO mezzanine as input or output. For
inputs, it provides an accurate UTC time stamp (using UTC from the
WRPC, not shown in the diagram) and optionally a host (PCIe)
interrupt via the IRQ Gen block. For outputs, it allows the user to
schedule the generation of a pulse at a given future UTC time, or to
generate it immediately.
The Interrupt Request
(IRQ Gen) block receives one-tick-long pulses from other blocks and
generates interrupt requests to the GN4124 core. It also includes
interrupt source and mask registers.
(WB intercon) block ensures seamless interconnection of Wishbone
masters and slaves using a crossbar topology.
The GN4124 core is
a bridge between the GN4124 PCIe interface chip and the internal
Wishbone bus, allowing communication with the host and interrupts.
The White Rabbit PTP
communicates with the outside world through the SFP socket in the
SPEC, typically using fiber optics. It deals with the WR PTP using
an internal soft-CPU running a PTP stack. It
forwards/receives non-PTP frames to/from the NIC block, using two
pipelined Wishbone interfaces (master and slave for forwarding and
receiving respectively). It also provides UTC time to other cores
(not represented in the diagram), and time-tags for transmitted and
received frames that can be read through Wishbone for diagnostics
The Network Interface
(NIC) core ensures communication between the host and the WRPC. More
precisely, it interrupts the host and provides a descriptor that the
host can use to fetch incoming frames. For outgoing frames, it
receives a descriptor from the host, fetches the frame using PCIe
DMA via the GN4124 core and sends it to the WRPC using a pipelined
The TxTSU module collects timestamps with associated Ethernet frame
identifiers and puts them in a shared FIFO.
The Etherbone (EB)
core is a component that allows remote device configuration through
the network using UDP packets. Thanks to this, a standalone mode can
be implemented for the WR-NIC. So, the WR-NIC can be used as a
coprocessor board plugged in a PCIe slot of a conventional computer
or can work autonomously as a node of the White Rabbit network.
The Multiplexer (MUX) core routes the incoming packets to the
Etherbone or NIC component depending on its class. Each received
packet from the network is classified by the WRPC to decide which is
the component that will process it. For this reason, the software
for the WRPC must be modified in order to set the different classes
and the rules to identify them.
This project focus on the HDL but it is currently fully supported in
terms of additional software (board drivers, applications examples,
etc...) as well as documentation. Please check the White Rabbit
Starting kit project
for additional details.
Add the DMA support in order to improve the performance
Note: The current gateware version is indicated in bold.
A caution to be considered in current release is that the first DIO
FMC output channel is reserved for 1-PPS signal from the WRPC. This is
the simplest way to avoid the delay between the 1-PPS input and 1-PPS
output when the Grand Master mode is used.