adding Manifests, ISE project file and empty top files

0ea1321a · Grzegorz Daniluk · 12278634 · 0ea1321a · 0ea1321a · 0ea1321a
Commit 0ea1321a authored Feb 08, 2012 by Grzegorz Daniluk
6 changed files
--- a/Manifest.py
+++ b/Manifest.py
+fetchto = "ip_cores"
+
+modules =  {"local" : 
+    [ "modules/wrsw_nic" ],
+    "git" : "git://ohwr.org/hdl-core-lib/wr-cores.git::wrcore_v2",
+    "svn" : "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl"
+    }
--- a/syn/spec/Manifest.py
+++ b/syn/spec/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_top = "wr_nic_top"
+syn_project = "wr_nic.xise"
+
+modules = { "local" : [ "../../top/spec" ] }
--- a/syn/spec/wr_nic.xise
+++ b/syn/spec/wr_nic.xise
--- a/top/spec/Manifest.py
+++ b/top/spec/Manifest.py
+files = ["wr_nic_top.vhd", "wr_nic_top.ucf" ]
+
+fetchto = "../../ip_cores"
+
+modules = {
+					 "local" : ["../../"]
+					}
--- a/top/spec/wr_nic_top.ucf
+++ b/top/spec/wr_nic_top.ucf
--- a/top/spec/wr_nic_top.vhd
+++ b/top/spec/wr_nic_top.vhd