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......@@ -72,60 +72,23 @@ set up a WR DDS test system.
## Status
<table>
<tbody>
<tr class="odd">
<td><strong>Date</strong></td>
<td><b> Event </b></td>
</tr>
<tr class="even">
<td>01-04-2013</td>
<td>Project started.</td>
</tr>
<tr class="odd">
<td>03-04-2013</td>
<td>Specification ready.</td>
</tr>
<tr class="even">
<td>10-04-2013</td>
<td>V0 schematics created &amp; reviewed.</td>
</tr>
<tr class="odd">
<td>15-04-2013</td>
<td>FMC hardware order sent to company.</td>
</tr>
<tr class="even">
<td>20-04-2013</td>
<td>Started VHDL/software development.</td>
</tr>
<tr class="odd">
<td>24-04-2013</td>
<td>Received &amp; powered up 2 [DDS mezzanines](https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds).</td>
</tr>
<tr class="even">
<td>08-05-2013</td>
<td>First working <a href="/RF-distribution-demo">demo</a> design.</td>
</tr>
<tr class="odd">
<td>15-05-2013</td>
<td><a href="/RF-distribution-demo">2013 Demo</a> presented on PH-ESE seminar.</td>
</tr>
<tr class="even">
<td>20-10-2015</td>
<td>Mock Turtle-based RF distribution system presented on ICALEPCS' 2015.</td>
</tr>
<tr class="odd">
<td>01-12-2015</td>
<td>Project specification extended to include SPS ion RF clock.</td>
</tr>
<tr class="even">
<td>20-01-2016</td>
<td>Successful simulation of distributing SPS ion RF clock using undersampling ADC.</td>
</tr>
</tbody>
</table>
|**Date**|**Event **|
|----|----|
|01-04-2013|Project started.|
|03-04-2013|Specification ready.|
|10-04-2013|V0 schematics created & reviewed.|
|15-04-2013|FMC hardware order sent to company.|
|20-04-2013|Started VHDL/software development.|
|24-04-2013|Received & powered up 2 [DDS mezzanines](https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds).|
|08-05-2013|First working [demo](/RF-distribution-demo) design.|
|15-05-2013|[2013 Demo](/RF-distribution-demo) presented on PH-ESE seminar.|
|20-10-2015|Mock Turtle-based RF distribution system presented on ICALEPCS' 2015.|
|01-12-2015|Project specification extended to include SPS ion RF clock.|
|20-01-2016|Successful simulation of distributing SPS ion RF clock using undersampling ADC.|
-----
Tomasz Wlostowski - 21 January 2016