WR Streamers
WR Streamers provide to the user a FIFO-like interface over Ethernet. WR Streamers comprise of two VHDL modules to send and receive data:
- TX steamer takes a series of data words and encapsulates them into Ethernet Frames
- RX streamer does the opposite: decodes Ethernet frames into series of data words
User interface of a TX-RX streamer pair looks like a typical FIFO, with an Ethernet link inside.
Interface of Tx and Rx Streamer modules
Streamers principles
- Streamers transfer data words and transparently encapsulate them into Ethernet frames
- Data words can have width of n * 16 bits (generic: g_data_width)
- Data words can be grouped in blocks of arbitrary size
- Each block has independent sequence number and CRC