WhiteRabbit PTP core on VFC-HD (generics and ports)

Module Generics

There are five generics provided for the parametrisation of the module.

Module Ports

The following table lists all the input/output ports of the module. Note that depending on the values of the module generics (g_fabric_iface in particular), not all ports are required.

1. SFP is detected (plugged in)
2. The part number has been successfully read after the SFP detection| |sfp_data_i|in|std_logic_vector|The VFC-HD board implements I2C multiplexers to provide access to the numerous SFP interfaces (as well as other I2C-controlled peripherals). The VFC-HD project provides an additional module (in Verilog) which takes care of accessing the SFP information and making it available to the WR PTP code, in the form of a 16 byte vendor Part Number (128 bits std_logic_vector, ASCII encoded, first character byte in bits 127 downto 120).| |I2C EEPROM| |eeprom_sda_b|inout|std_logic|Bidirectional I2C SDA line.| |eeprom_scl_o|out|std_logic|Normally, this should also be bidirectional, but VFC-HD defines SCL as output, which works because the EEPROM is the only device connected on this I2C bus.| |Onewire interface| |onewire_i|in|std_logic|Data input from the onewire interface.| |onewire_oen_o|out|std_logic|Output enable to the onewire interface. When this is asserted, the instantiating module should drive the onewire data output to ground.| |External WB interface| |wb_adr_i|in|std_logic_vector|Wishbone slave interface, operating in "Pipelined" mode, with word granularity. It provides access to all the Wishbone peripherals inside the WR PTP core. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).| |wb_dat_i|in|std_logic_vector| |wb_dat_o|out|std_logic_vector| |wb_sel_i|in|std_logic_vector| |wb_we_i|in|std_logic| |wb_cyc_i|in|std_logic| |wb_stb_i|in|std_logic| |wb_ack_o|out|std_logic| |wb_int_o|out|std_logic| |wb_err_o|out|std_logic| |wb_rty_o|out|std_logic| |wb_stall_o|out|std_logic| |**WR fabric interface **| |wrf_src_adr_o|out|std_logic_vector|Pipelined Wishbone master interface. It passes all the Ethernet frames received from a physical link to a slave interface implemented in a user-defined module. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).| |wrf_src_dat_o|out|std_logic_vector| |wrf_src_cyc_o|out|std_logic| |wrf_src_stb_o|out|std_logic| |wrf_src_we_o|out|std_logic| |wrf_src_sel_o|out|std_logic_vector| |wrf_src_ack_i|in|std_logic| |wrf_src_stall_i|in|std_logic| |wrf_src_err_i|in|std_logic| |wrf_src_rty_i|in|std_logic| |wrf_snk_adr_i|in|std_logic_vector|Pipelined Wishbone slave interface. It receives Ethernet frames from a master interface implemented in a user-defined module, and sends them to a physical link. VHDL records are not used here, to facilitate integration of the module into Verilog-based projects (such as the VFC-HD).| |wrf_snk_dat_i|in|std_logic_vector| |wrf_snk_cyc_i|in|std_logic| |wrf_snk_stb_i|in|std_logic| |wrf_snk_we_i|in|std_logic| |wrf_snk_sel_i|in|std_logic_vector| |wrf_snk_ack_o|out|std_logic| |wrf_snk_stall_o|out|std_logic| |wrf_snk_err_o|out|std_logic| |wrf_snk_rty_o|out|std_logic| |**WR streamers **| |wrs_tx_data_i|in|std_logic_vector|Data word to be sent over the physical link. The width of the vector is equal to g_streamer_width parameter.| |wrs_tx_valid_i|in|std_logic|An '1' indicates that the tx_data_i contains a valid data word.| |wrs_tx_dreq_o|out|std_logic|Synchronous data request: when '1', the user may send a data word in the following clock cycle.| |wrs_tx_last_i|in|std_logic|An '1' indicates the last data word in a larger block of samples.| |wrs_tx_flush_i|in|std_logic|When asserted, the streamer will immediately send out all the data that is stored in its TX buffer.| |wrs_rx_first_o|out|std_logic|An '1' indicates the first data word of the data block on wrs_rx_data_o.| |wrs_rx_last_o|out|std_logic|An '1' indicates the last data word of the data block on wrs_rx_data_o.| |wrs_rx_data_o|out|std_logic_vector|Data word received from the physical link. The width of the vector is equal to g_streamer_width parameter.| |wrs_rx_valid_o|out|std_logic|An '1' indicates that rx_data_o is outputting a valid data word.| |wrs_rx_dreq_i|in|std_logic|Synchronous data request input: when '1', the streamer may output another data word in the subsequent clock cycle.| |WRPC timing interface and status| |pps_p_o|out|std_logic|1-PPS (Pulse Per Second) signal generated in the clk_ref_125m_o clock domain and aligned to WR time, pulse generated when the cycle counter is 0 (beginning of each full TAI second).| |tm_time_valid_o|out|std_logic|If 1, the timecode generated by the WRPC is valid.| |tm_tai_o|out|std_logic_vector|TAI part of the timecode (40 bits).| |tm_cycles_o|out|std_logic_vector|Fractional part of each second represented by the state of counter clocked with the frequency 125 MHz (values from 0 to 124999999, each count is 8 ns).| |led_link_o|out|std_logic|signal for driving Ethernet Link LED.| |led_act_o|out|std_logic|signal for driving Ethernet Act LED.|

20 December 2016