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Peter Jansweijer authored
added delta delays in phy output signals to line up with the ch#_rx_rbclk_o assignment (purely necessary for proper simulation only)
d7afa48e
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chipscope | ||
wr_gtp_phy | ||
Manifest.py | ||
ext_pll_10_to_125m.vhd | ||
wr_xilinx_pkg.vhd |