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Maciej Lipinski authored
oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/ that include generic modules. This prevented the Altera-based design from building. Ultimately, the module needs to be moved to some more appropriate place, possibly to general-cores/platform/xilinx. To be decided. A temporary solution is to have it in board/cute, since it is only used by in the xwrc_board_cute.
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fabric | ||
timing | ||
wr_dacs | ||
wr_eca | ||
wr_endpoint | ||
wr_mini_nic | ||
wr_nic | ||
wr_pps_gen | ||
wr_si57x_interface | ||
wr_softpll_ng | ||
wr_streamers | ||
wr_tbi_phy | ||
wr_tlu | ||
wr_txtsu | ||
wrc_core | ||
Manifest.py |