wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resets

wr_board_pkg: declare eb_ethernet_slave as a component so that compiler doesn't complain when EB repo is not included

Compilation and synthesis run at any new push. Simulation run according
to CI schedule configured on OHWR.

upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd

add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout)
wrc_phy16_direct_dmtd.bram build with:
wrpc-sw.git peter_direct_dmtd SHA 50f1c0e
ppsi.git peter_direct_dmtd SHA bf5f6de