Commit 83501b68 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'peter_clbv2_3_4_ref_design_191119' into proposed_master

parents faf5e9a3 2b4daa08
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try:
if board in ["spec", "svec", "vfchd", "common"]:
if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "common"]:
modules = {"local" : [ board ] }
except NameError:
pass
......@@ -282,6 +282,8 @@ package wr_clbv2_pkg is
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
......
......@@ -287,6 +287,8 @@ package wr_clbv3_pkg is
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
......
files = [
"wr_clbv4_pkg.vhd",
"xwrc_board_clbv4.vhd",
"wrc_board_clbv4.vhd",
]
modules = {
"local" : [
"../common",
]
}
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board = "clbv2"
target = "xilinx"
action = "synthesis"
......@@ -6,8 +7,8 @@ syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv2_wr_ref_top"
syn_project = "clbv2_wr_ref.xise"
syn_project = "clbv2_wr_ref.xpr"
syn_tool = "ise"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv2_ref_design/"}
This diff is collapsed.
board = "clbv3"
target = "xilinx"
action = "synthesis"
......@@ -6,8 +7,8 @@ syn_grade = "-2"
syn_package = "fbg484"
syn_top = "clbv3_wr_ref_top"
syn_project = "clbv3_wr_ref.xise"
syn_project = "clbv3_wr_ref.xpr"
syn_tool = "ise"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv3_ref_design/"}
This diff is collapsed.
board = "clbv4"
target = "xilinx"
action = "synthesis"
syn_device = "xc7k160t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv4_wr_ref_top"
syn_project = "clbv4_wr_ref.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv4_ref_design/"}
......@@ -2,14 +2,13 @@ fetchto = "../../ip_cores"
files = [
"clbv2_wr_ref_top.vhd",
"clbv2_wr_ref_top.ucf",
"clbv2_wr_ref_top.xdc",
"clbv2_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv2",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
......
......@@ -30,38 +30,38 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv2/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
This diff is collapsed.
......@@ -8,7 +8,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 2017-11-08
-- Last update: 2019-06-28
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CLBv2.
......@@ -54,14 +54,16 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv2_pkg.all;
--use work.gn4124_core_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv2_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy16.bram";
g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16.bram";
-- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
-- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
......@@ -125,11 +127,20 @@ entity clbv2_wr_ref_top is
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
led_link_o : out std_logic;
-- Reset control
reset_i : in std_logic;
suicide : out std_logic;
reset_i : in std_logic;
-- Monitoring signals output on test-pads and External Debug Connector J35
pll_oe_out_b : out std_logic;
pps_p : out std_logic;
pps_n : out std_logic;
ref_clk_p : out std_logic;
ref_clk_n : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
......@@ -176,35 +187,6 @@ end entity clbv2_wr_ref_top;
architecture top of clbv2_wr_ref_top is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
-- Number of slaves on the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_ETHBONE : integer := 1;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
......@@ -248,12 +230,13 @@ architecture top of clbv2_wr_ref_top is
begin -- architecture top
suicide<= '1';
reset_n <= not reset_i; -- Reset = high active on CLB
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
reset_n <= not reset_i; -- Reset = high active on CLB
cmp_xwrc_board_clbv2 : xwrc_board_clbv2
generic map (
g_simulation => g_simulation,
......@@ -338,13 +321,13 @@ begin -- architecture top
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 3 as outputs
-- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- All DIO connectors are not terminated
dio_term_en_o <= (others => '0');
-- Configure Digital I/Os 3 to 4 inputs to be terminated.
dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
......@@ -373,6 +356,21 @@ begin -- architecture top
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
-- Enable test-pad TP17, TP18 driver
pll_oe_out_b <= '0';
U_pps_mon_obuf : OBUFDS
port map (
I => wrc_pps_out,
O => pps_p,
OB => pps_n);
U_ref_clk_mon_obuf : OBUFDS
port map (
I => clk_ref_62m5,
O => ref_clk_p,
OB => ref_clk_n);
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
......
......@@ -2,14 +2,13 @@ fetchto = "../../ip_cores"
files = [
"clbv3_wr_ref_top.vhd",
"clbv3_wr_ref_top.ucf",
"clbv3_wr_ref_top.xdc",
"clbv3_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
"../../board/clbv3",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
......
......@@ -29,39 +29,39 @@
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram38 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram37 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram36 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram35 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram34 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram33 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram32 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram31 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram28 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram27 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram26 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram25 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram24 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram23 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram22 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram21 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram18 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram17 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram16 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram15 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram14 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram13 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram12 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram11 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram08 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram07 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram06 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram05 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram04 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram03 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram02 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/Mram_ram01 [0];
BUS_BLOCK
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv3/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
fetchto = "../../ip_cores"
files = [
"clbv4_wr_ref_top.vhd",
"clbv4_wr_ref_top.xdc",
"clbv4_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
/* FILE : clbv4_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm clbv4_wr_ref_top_bd.bmm -bt clbv4_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
This diff is collapsed.
This diff is collapsed.
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