- 31 Jul, 2012 2 commits
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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- 26 Jul, 2012 2 commits
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Tomasz Wlostowski authored
platform/xilinx/wr_gtx_phy_virtex6: generic parameter for choice between global and regional clock buffers on RX clock
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Tomasz Wlostowski authored
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- 24 Jul, 2012 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 16 Jul, 2012 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 12 Jul, 2012 1 commit
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Grzegorz Daniluk authored
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- 10 Jul, 2012 4 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
However, timing constraints start failing.
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Tomasz Wlostowski authored
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- 09 Jul, 2012 14 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Stefan Rauch authored
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Stefan Rauch authored
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Wesley W. Terpstra authored
=> needed for preloaded firmware (ie: production cards) => needed to program firmware over JTAG
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Wesley W. Terpstra authored
=> needed for gdb connection => needed for loading LM32 firmware over JTAG
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 06 Jul, 2012 4 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
wr_endpoint: re-generated WB slave, replaced VLAN/PFilter registers by RW/RW types which get synthesized away when not used
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Tomasz Wlostowski authored
wr_endpoint/ep_clock_alignment_fifo: use HW-generated almost_empty flag instead of comparison of word counter with pass_threshold (less resources)
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- 03 Jul, 2012 8 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
Forgot to use the xilinx specific package in the spec.
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Stefan Rauch authored
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Stefan Rauch authored
Update the SCU usage of the wrcore (and attached SFP) Move the pow_reset and flash_loader into altera platform components
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Stefan Rauch authored
* Added the new SCU2 target (different pinouts and components) * Moved common components (uart) to modules * Moved the common spec and SCU DAC files into modules * Added the DDR3 controller for Altera * Removed a few superfluous files from version control
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Stefan Rauch authored
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