- 13 Jan, 2015 10 commits
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Grzegorz Daniluk authored
Based on Peter's work, ported to current wr_endpoint code.
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Grzegorz Daniluk authored
wr_endpoint/ep_rx_path: don't instantiate U_match_buffer when neither early match nor pfilter are there
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Grzegorz Daniluk authored
Otherwise, FSM cannot react on time under a storm of traffic.
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Grzegorz Daniluk authored
When it was doing that, for short frames pclass and drop_o were zeroed and U_match_buffer was not getting correct values.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Although fab_dreq is low in FINISH_CYCLE state, ep_rx_buffer outputs SOF in the same cycle it gets fab_dreq low. That means we may get SOF while still in FINISH_CYCLE state, and we lose it if not stored in a register.
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Peter Jansweijer authored
Precision synthesis complains "Error: Net is driven by multiple primitive gates -- NET: regs_towb_dmcr_n_avg_i(11:0)" This is due to the fact that when g_with_dmtd is true then "regs_towb.dmcr_n_avg_i" was driven. This signal should be orred as the rest of regs_towb assignment.
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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- 09 Jan, 2015 4 commits
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Theodor-Adrian Stana authored
The outputs to the SPI interface from wrc_periph were not clocked, which led to improper operation. This error was now fixed and everything seems to work fine.
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Grzegorz Daniluk authored
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Theodor-Adrian Stana authored
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
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Grzegorz Daniluk authored
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- 08 Jan, 2015 1 commit
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Mathias Kreider authored
WB slave interface auto-generated by wbgenplus
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- 23 Dec, 2014 1 commit
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Stefan Rauch authored
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- 09 Dec, 2014 5 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Conflicts: top/spec_1_1/wr_core_demo/spec_top.vhd
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Conflicts: modules/wr_endpoint/ep_tx_pcs_8bit.vhd modules/wr_softpll_ng/wr_softpll_ng.vhd
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Tomasz Wlostowski authored
Explanation: - the busy flag is asserted whenever the TX state machine is not idle (e.g not in TX_IDLE or TX_COMMA state) or if the TX FIFO is not empty - since the TX FSM works in different clock domain than the system clock, where the busy flag is outputted, there is a synchronizer - The Heisenbug appeared in designs where TX clock is phase locked to the system clock (e.g. SPEC/SVEC). It was caused by a cross-clock domain setup time violation between the output of the LUT generating the tx_busy signal and the first flip flop of the synchronizer, which under certain conditions could permanently sample incorrect output of the LUT, resulting with the pcs_busy_o signal being stuck at 1 forever. - registering the TX clock domain busy signal removes glitches and fixes the problem.
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- 28 Nov, 2014 1 commit
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Grzegorz Daniluk authored
We can have it together with rst_synced_refclk because in that case pps_valid will become 1 automatically after 2 PPS pulses.
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- 17 Nov, 2014 1 commit
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Grzegorz Daniluk authored
Built from wrpc-sw fc63d9cf
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- 14 Nov, 2014 3 commits
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Grzegorz Daniluk authored
In reverse dmtd mode, only first flip-flop should be sampling dmtd clk with clk_in. That's done inside dmtd_with_deglitcher. Earlier the clocks were swapped so the whole chain of flip-flops was clocked with clk_in which was wrong.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 22 Jul, 2014 2 commits
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Grzegorz Daniluk authored
In reverse dmtd mode, only first flip-flop should be sampling dmtd clk with clk_in. That's done inside dmtd_with_deglitcher. Earlier the clocks were swapped so the whole chain of flip-flops was clocked with clk_in which was wrong.
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Grzegorz Daniluk authored
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- 17 Jul, 2014 5 commits
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Tomasz Wlostowski authored
Conflicts: ip_cores/etherbone-core ip_cores/general-cores ip_cores/gn4124-core modules/wrc_core/wrcore_pkg.vhd modules/wrc_core/xwr_core.vhd syn/spec_1_1/wr_core_demo/Manifest.py syn/spec_1_1/wr_core_demo/spec_top_wrc.xise
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Wesley W. Terpstra authored
The softpll_ng takes in a reset line from the sys clock domain. It instantiates several dmtd_with_deglitcher FSMs which need reset. The symptom of this bug is that on 3% of power-ups, some of the deglitchers will not issue tags, because they power-on into an undefined FSM state. This is caused by feeding the reset from a different clock domain, leading to a race condition on release. There was some code that probably used to solve this issue, whereby the sys reset was synchronized to the clk_dmtd_i. However, the softpll_ng instantiates multiple deglitchers, each in a different domain and thus this single synchronizer chain can not work for all of the deglitcher instances. The fix is simple: synchronize the reset for each clock domain.
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Maciej Lipinski authored
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Maciej Lipinski authored
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Tomasz Wlostowski authored
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- 24 Jun, 2014 1 commit
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Wesley W. Terpstra authored
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- 23 Jun, 2014 1 commit
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Mathias Kreider authored
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- 18 Jun, 2014 2 commits
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Wesley W. Terpstra authored
The symptom of this bug is that about 3% of the time a WR endpoint will power-up such that it always fails to reach track phase state. This is caused by the endpoint dropping the first PTP packet after calibration. The packet is dropped, because it is misclassified. This happens because it is possible for the U_match_buffer and fab_pipe in the RX path to become desynchronized. When this happens, packets receive the classification of the previous packet. Since calibration is slow, it is virtually assured that a BOOTP request is seen, leading to the misclassification of the following PTP packet. The U_match_buffer can become desynchronized multiple ways, but the one we saw "in the wild" is due to the lowering of PFCR0 in wrpc-sw during packet filter configuration. Due to an unsafe transfer from clk_sys to clk_rx in ep_packet_filter:p_gen_status, it is possible for the transition of PFCR0 to cause a glitch that sets done_int high, even though there is no packet being processed. This puts an excess class tag into U_match_buffer, which leads to the mismatch between packets and classes. This patch fixes the transfer. Unfortunately, even after this patch, it is my opinion that this code remains completely unsafe. The core problem is that desynchronization of U_match_buffer and fab_pipe is possible at all. This is a very brittle design. One can imagine many scenarios that can lead to this state, after which point the WR endpoint will never recover. A simple example: consider a packet arriving while PFCR0 is switched. ep_rx_path:mbuf_we can then pulse twice, once, or never for the packet depending on the race condition between ematch_done and pfilter_done. If this happens, the RX path will remain permanently desynchronized.
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Wesley W. Terpstra authored
The softpll_ng takes in a reset line from the sys clock domain. It instantiates several dmtd_with_deglitcher FSMs which need reset. The symptom of this bug is that on 3% of power-ups, some of the deglitchers will not issue tags, because they power-on into an undefined FSM state. This is caused by feeding the reset from a different clock domain, leading to a race condition on release. There was some code that probably used to solve this issue, whereby the sys reset was synchronized to the clk_dmtd_i. However, the softpll_ng instantiates multiple deglitchers, each in a different domain and thus this single synchronizer chain can not work for all of the deglitcher instances. The fix is simple: synchronize the reset for each clock domain.
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- 12 Jun, 2014 3 commits
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Grzegorz Daniluk authored
Under higher load of traffic SOF was being detected while main FSM was not yet done with sending frame. That caused OOB FSM to reset and "tx timestamp never became available" warnings in WR PTP Core software.
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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