wr_endpoint/ep_1000basex_pcs.vhd: connect serdes loopback enable signal to PCS register block

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

wr_endpoint/ep_1000basex_pcs.vhd: connect serdes loopback enable signal to PCS register block
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
ff5337e9 · Tomasz Wlostowski · Grzegorz Daniluk · 055d60af · ff5337e9
Commit ff5337e9 authored Jun 03, 2013 by Tomasz Wlostowski Committed by Grzegorz Daniluk Jun 04, 2013
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ep_1000basex_pcs.vhd modules/wr_endpoint/ep_1000basex_pcs.vhd +4 -1

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--- a/modules/wr_endpoint/ep_1000basex_pcs.vhd
+++ b/modules/wr_endpoint/ep_1000basex_pcs.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2012-03-16
+-- Last update: 2013-06-03
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -657,4 +657,7 @@ begin  -- rtl
  end process;

  link_ok_o <= link_ok and synced;
+
+  serdes_loopen_o <= mdio_mcr_loopback;
+
 end rtl;