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White Rabbit core collection
Commit f3298f17 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_pps_gen: writing ESCR.SYNC=0 should disable external PPS resynchronization

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modules/wr_pps_gen/wr_pps_gen.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2013-07-26
-- Last update: 2013-08-05
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -63,7 +63,7 @@ entity wr_pps_gen is
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_led_o : out std_logic;
pps_led_o : out std_logic;
pps_valid_o : out std_logic;
......@@ -111,8 +111,8 @@ architecture behavioral of wr_pps_gen is
ppsg_escr_sync_load_o : out std_logic;
ppsg_escr_pps_valid_o : out std_logic;
ppsg_escr_tm_valid_o : out std_logic;
ppsg_escr_sec_set_o : out std_logic;
ppsg_escr_nsec_set_o : out std_logic);
ppsg_escr_sec_set_o : out std_logic;
ppsg_escr_nsec_set_o : out std_logic);
end component;
......@@ -140,8 +140,8 @@ architecture behavioral of wr_pps_gen is
signal ppsg_escr_sync_load : std_logic;
signal ppsg_escr_sync_in : std_logic;
signal ppsg_escr_sync_out : std_logic;
signal ppsg_escr_sec_set : std_logic;
signal ppsg_escr_nsec_set : std_logic;
signal ppsg_escr_sec_set : std_logic;
signal ppsg_escr_nsec_set : std_logic;
signal ppsg_escr_pps_valid : std_logic;
signal ppsg_escr_tm_valid : std_logic;
......@@ -181,8 +181,8 @@ architecture behavioral of wr_pps_gen is
signal pps_valid_int : std_logic;
signal pps_out_int : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
......@@ -343,8 +343,8 @@ begin -- behavioral
sync_in_progress <= '0';
ppsg_escr_sync_in <= '0';
else
if(ppsg_escr_sync_load = '1' and ppsg_escr_sync_out = '1') then
sync_in_progress <= '1';
if(ppsg_escr_sync_load = '1') then
sync_in_progress <= ppsg_escr_sync_out;
ppsg_escr_sync_in <= '0';
end if;
......@@ -491,19 +491,19 @@ begin -- behavioral
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
pps_out_int <= '0';
pps_led_o <= '0';
pps_led_o <= '0';
width_cntr <= (others => '0');
else
if(ns_overflow_adv = '1') then
pps_out_int <= ppsg_escr_pps_valid;
width_cntr <= unsigned(ppsg_cr_pwidth);
elsif(ns_overflow = '1') then
pps_led_o <= ppsg_escr_pps_valid;
elsif(ns_overflow = '1') then
pps_led_o <= ppsg_escr_pps_valid;
else
if(width_cntr = to_unsigned(0, width_cntr'length)) then
pps_out_int <= '0';
pps_led_o <= '0';
pps_led_o <= '0';
else
width_cntr <= width_cntr -1;
end if;
......@@ -515,11 +515,11 @@ begin -- behavioral
process(clk_ref_i, rst_synced_refclk)
begin
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
pps_out_o <= '0';
if rising_edge(clk_ref_i) then
if rst_synced_refclk = '0' then
pps_out_o <= '0';
else
pps_out_o <= pps_out_int;
pps_out_o <= pps_out_int;
end if;
end if;
end process;
......@@ -560,8 +560,8 @@ begin -- behavioral
ppsg_adj_utchi_wr_o => ppsg_adj_utchi_wr,
ppsg_escr_pps_valid_o => ppsg_escr_pps_valid,
ppsg_escr_tm_valid_o => ppsg_escr_tm_valid,
ppsg_escr_sec_set_o => ppsg_escr_sec_set,
ppsg_escr_nsec_set_o => ppsg_escr_nsec_set);
ppsg_escr_sec_set_o => ppsg_escr_sec_set,
ppsg_escr_nsec_set_o => ppsg_escr_nsec_set);
-- start the adjustment upon write of 1 to CNT_ADJ bit
cntr_adjust_p <= ppsg_cr_cnt_adj_load and ppsg_cr_cnt_adj_o;
......
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