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White Rabbit core collection
Commit def59fe9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_pps_gen: ESCR.SEC_SET and ESCR.NSEC_SET are in reference clock domain

parent 99bb4b6b
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Showing with 39 additions and 17 deletions
modules/wr_pps_gen/pps_gen_wb.vhd
View file @ def59fe9
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created : Fri Jul 26 15:09:09 2013
-- Created : Mon Aug 5 12:04:01 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
......@@ -63,9 +63,9 @@ entity pps_gen_wb is
ppsg_escr_pps_valid_o : out std_logic;
-- Port for asynchronous (clock: refclk_i) BIT field: 'Timecode output(UTC+cycles) valid' in reg: 'External sync control register'
ppsg_escr_tm_valid_o : out std_logic;
-- Port for MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set seconds counter' in reg: 'External sync control register'
ppsg_escr_sec_set_o : out std_logic;
-- Port for MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
-- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
ppsg_escr_nsec_set_o : out std_logic
);
end pps_gen_wb;
......@@ -136,10 +136,16 @@ signal ppsg_escr_pps_valid_sync1 : std_logic ;
signal ppsg_escr_tm_valid_int : std_logic ;
signal ppsg_escr_tm_valid_sync0 : std_logic ;
signal ppsg_escr_tm_valid_sync1 : std_logic ;
signal ppsg_escr_sec_set_dly0 : std_logic ;
signal ppsg_escr_sec_set_int : std_logic ;
signal ppsg_escr_nsec_set_dly0 : std_logic ;
signal ppsg_escr_sec_set_int_delay : std_logic ;
signal ppsg_escr_sec_set_sync0 : std_logic ;
signal ppsg_escr_sec_set_sync1 : std_logic ;
signal ppsg_escr_sec_set_sync2 : std_logic ;
signal ppsg_escr_nsec_set_int : std_logic ;
signal ppsg_escr_nsec_set_int_delay : std_logic ;
signal ppsg_escr_nsec_set_sync0 : std_logic ;
signal ppsg_escr_nsec_set_sync1 : std_logic ;
signal ppsg_escr_nsec_set_sync2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -200,7 +206,9 @@ begin
ppsg_escr_pps_valid_int <= '0';
ppsg_escr_tm_valid_int <= '0';
ppsg_escr_sec_set_int <= '0';
ppsg_escr_sec_set_int_delay <= '0';
ppsg_escr_nsec_set_int <= '0';
ppsg_escr_nsec_set_int_delay <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -210,8 +218,6 @@ begin
ppsg_adj_nsec_wr_o <= '0';
ppsg_adj_utclo_wr_o <= '0';
ppsg_adj_utchi_wr_o <= '0';
ppsg_escr_sec_set_int <= '0';
ppsg_escr_nsec_set_int <= '0';
ack_in_progress <= '0';
else
ppsg_cr_cnt_rst_int <= ppsg_cr_cnt_rst_int_delay;
......@@ -253,6 +259,10 @@ begin
rddata_reg(0) <= ppsg_escr_sync_int_read;
ppsg_escr_sync_lw_read_in_progress <= '0';
end if;
ppsg_escr_sec_set_int <= ppsg_escr_sec_set_int_delay;
ppsg_escr_sec_set_int_delay <= '0';
ppsg_escr_nsec_set_int <= ppsg_escr_nsec_set_int_delay;
ppsg_escr_nsec_set_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -468,7 +478,9 @@ begin
ppsg_escr_pps_valid_int <= wrdata_reg(1);
ppsg_escr_tm_valid_int <= wrdata_reg(2);
ppsg_escr_sec_set_int <= wrdata_reg(3);
ppsg_escr_sec_set_int_delay <= wrdata_reg(3);
ppsg_escr_nsec_set_int <= wrdata_reg(4);
ppsg_escr_nsec_set_int_delay <= wrdata_reg(4);
end if;
if (wb_we_i = '0') then
rddata_reg(0) <= 'X';
......@@ -755,27 +767,35 @@ begin
-- Set seconds counter
process (clk_sys_i, rst_n_i)
process (refclk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ppsg_escr_sec_set_dly0 <= '0';
ppsg_escr_sec_set_o <= '0';
elsif rising_edge(clk_sys_i) then
ppsg_escr_sec_set_dly0 <= ppsg_escr_sec_set_int;
ppsg_escr_sec_set_o <= ppsg_escr_sec_set_int and (not ppsg_escr_sec_set_dly0);
ppsg_escr_sec_set_sync0 <= '0';
ppsg_escr_sec_set_sync1 <= '0';
ppsg_escr_sec_set_sync2 <= '0';
elsif rising_edge(refclk_i) then
ppsg_escr_sec_set_sync0 <= ppsg_escr_sec_set_int;
ppsg_escr_sec_set_sync1 <= ppsg_escr_sec_set_sync0;
ppsg_escr_sec_set_sync2 <= ppsg_escr_sec_set_sync1;
ppsg_escr_sec_set_o <= ppsg_escr_sec_set_sync2 and (not ppsg_escr_sec_set_sync1);
end if;
end process;
-- Set nanoseconds counter
process (clk_sys_i, rst_n_i)
process (refclk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ppsg_escr_nsec_set_dly0 <= '0';
ppsg_escr_nsec_set_o <= '0';
elsif rising_edge(clk_sys_i) then
ppsg_escr_nsec_set_dly0 <= ppsg_escr_nsec_set_int;
ppsg_escr_nsec_set_o <= ppsg_escr_nsec_set_int and (not ppsg_escr_nsec_set_dly0);
ppsg_escr_nsec_set_sync0 <= '0';
ppsg_escr_nsec_set_sync1 <= '0';
ppsg_escr_nsec_set_sync2 <= '0';
elsif rising_edge(refclk_i) then
ppsg_escr_nsec_set_sync0 <= ppsg_escr_nsec_set_int;
ppsg_escr_nsec_set_sync1 <= ppsg_escr_nsec_set_sync0;
ppsg_escr_nsec_set_sync2 <= ppsg_escr_nsec_set_sync1;
ppsg_escr_nsec_set_o <= ppsg_escr_nsec_set_sync2 and (not ppsg_escr_nsec_set_sync1);
end if;
end process;
......
modules/wr_pps_gen/pps_gen_wb.wb
View file @ def59fe9
......@@ -198,6 +198,7 @@ peripheral {
write 0: no effect";
prefix = "SEC_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
......@@ -206,6 +207,7 @@ peripheral {
write 0: no effect";
prefix = "NSEC_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
};
......
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