modules/wrc_core: New generic parameter to set uart fifo size.

This change is necessary for network control/monitor tool in order to read the GUI command output. The GUI command output can not be stored into a 1024 bytes fifo.

modules/wrc_core: New generic parameter to set uart fifo size.
This change is necessary for network control/monitor tool in order to read the GUI command output. The GUI command output can not be stored into a 1024 bytes fifo.
d85255b3 · Miguel Jimenez Lopez · Grzegorz Daniluk · 35a77c9f · 76f2e5d9 · d85255b3
Commit d85255b3 authored Feb 04, 2014 by Miguel Jimenez Lopez Committed by Grzegorz Daniluk Feb 06, 2014
5 changed files
--- a/general-cores @ 76f2e5d9
+++ b/general-cores @ 76f2e5d9
-Subproject commit 97d2f3564b23a33d41778b39f609e82f73c9796d
+Subproject commit 76f2e5d9278f35134e06fbb47f6315cdd0b736b9
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -94,7 +94,8 @@ entity wr_core is
    g_address_granularity       : t_wishbone_address_granularity := WORD;
    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
    g_softpll_channels_config   : t_softpll_channel_config_array := c_softpll_default_channel_config;
-    g_softpll_enable_debugger   : boolean                        := false
+    g_softpll_enable_debugger   : boolean                        := false;
+    g_vuart_fifo_size           : integer                        := 1024
    );
  port(
    ---------------------------------------------------------------------------
@@ -723,9 +724,10 @@ begin
  -----------------------------------------------------------------------------
  PERIPH : wrc_periph
    generic map(
-      g_phys_uart    => g_phys_uart,
+      g_phys_uart       => g_phys_uart,
-      g_virtual_uart => g_virtual_uart,
+      g_virtual_uart    => g_virtual_uart,
-      g_mem_words    => g_dpram_size)
+      g_mem_words       => g_dpram_size,
+      g_vuart_fifo_size => g_vuart_fifo_size)
    port map(
      clk_sys_i   => clk_sys_i,
      rst_n_i     => rst_n_i,

--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -33,10 +33,11 @@ use work.sysc_wbgen2_pkg.all;
 entity wrc_periph is
  generic(
-    g_phys_uart    : boolean := true;
+    g_phys_uart       : boolean := true;
-    g_virtual_uart : boolean := false;
+    g_virtual_uart    : boolean := false;
-    g_cntr_period  : integer := 62500;
+    g_cntr_period     : integer := 62500;
-    g_mem_words    : integer := 16384   --in 32-bit words
+    g_mem_words       : integer := 16384;   --in 32-bit words
+    g_vuart_fifo_size : integer := 1024
    );
  port(
    clk_sys_i : in std_logic;
@@ -264,7 +265,8 @@ begin
      g_with_virtual_uart   => g_virtual_uart,
      g_with_physical_uart  => g_phys_uart,
      g_interface_mode      => PIPELINED,
-      g_address_granularity => BYTE
+      g_address_granularity => BYTE,
+      g_vuart_fifo_size     => g_vuart_fifo_size
      )
    port map(
      clk_sys_i => clk_sys_i,

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -190,10 +190,11 @@ package wrcore_pkg is
  component wrc_periph is
    generic(
-      g_phys_uart    : boolean := true;
+      g_phys_uart       : boolean := true;
-      g_virtual_uart : boolean := false;
+      g_virtual_uart    : boolean := false;
-      g_cntr_period  : integer := 62500;
+      g_cntr_period     : integer := 62500;
-      g_mem_words    : integer := 16384
+      g_mem_words       : integer := 16384;
+      g_vuart_fifo_size : integer := 1024
      );
    port(
      clk_sys_i   : in  std_logic;
@@ -296,7 +297,8 @@ package wrcore_pkg is
      g_address_granularity       : t_wishbone_address_granularity := BYTE;
      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
      g_softpll_channels_config   : t_softpll_channel_config_array := c_softpll_default_channel_config;
-      g_softpll_enable_debugger   : boolean                        := false
+      g_softpll_enable_debugger   : boolean                        := false;
+      g_vuart_fifo_size           : integer                        := 1024
      );
    port(
      clk_sys_i  : in std_logic;
@@ -395,7 +397,8 @@ package wrcore_pkg is
      g_address_granularity       : t_wishbone_address_granularity := WORD;
      g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
      g_softpll_channels_config   : t_softpll_channel_config_array := c_softpll_default_channel_config;
-      g_softpll_enable_debugger   : boolean                        := false
+      g_softpll_enable_debugger   : boolean                        := false;
+      g_vuart_fifo_size           : integer                        := 1024
      );
    port(
      ---------------------------------------------------------------------------

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -79,7 +79,8 @@ entity xwr_core is
    g_address_granularity       : t_wishbone_address_granularity := WORD;
    g_aux_sdb                   : t_sdb_device                   := c_wrc_periph3_sdb;
    g_softpll_channels_config   : t_softpll_channel_config_array := c_softpll_default_channel_config;
-    g_softpll_enable_debugger   : boolean                        := false
+    g_softpll_enable_debugger   : boolean                        := false;
+    g_vuart_fifo_size           : integer                        := 1024
    );
  port(
    ---------------------------------------------------------------------------
@@ -229,7 +230,8 @@ begin
      g_address_granularity       => g_address_granularity,
      g_aux_sdb                   => g_aux_sdb,
      g_softpll_channels_config   => g_softpll_channels_config,
-      g_softpll_enable_debugger   => g_softpll_enable_debugger)
+      g_softpll_enable_debugger   => g_softpll_enable_debugger,
+      g_vuart_fifo_size           => g_vuart_fifo_size)
    port map(
      clk_sys_i  => clk_sys_i,
      clk_dmtd_i => clk_dmtd_i,