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White Rabbit core collection
Commit 35a77c9f authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Merge branch 'one-topfile-to-rule-them-all' into proposed_master 

This branch adds changes needed to unify all the GSI form-factors.
parents b8aee73b 27a68a03
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Showing with 41 additions and 33 deletions
general-cores @ 97d2f356
Subproject commit 71e18c1a658f24387b1b14291226c26d5eb178bc
Subproject commit 97d2f3564b23a33d41778b39f609e82f73c9796d
modules/wr_eca/eca.vhd
View file @ 35a77c9f
......@@ -289,12 +289,12 @@ architecture rtl of eca is
end update;
impure function toggle(x : std_logic; i : natural) return std_logic is
variable v_set : std_logic := c_slave_i.dat(i+0) and c_slave_i.sel(0);
variable v_clr : std_logic := c_slave_i.dat(i+8) and c_slave_i.sel(1);
constant c_set : std_logic := c_slave_i.dat(i+0) and c_slave_i.sel(0);
constant c_clr : std_logic := c_slave_i.dat(i+8) and c_slave_i.sel(1);
begin
return ((not v_set) and (not v_clr) and ( x)) or -- unmodified
(( v_set) and ( v_clr) and (not x)) or -- toggled
(( v_set) and (not v_clr)); -- set
return ((not c_set) and (not c_clr) and ( x)) or -- unmodified
(( c_set) and ( c_clr) and (not x)) or -- toggled
(( c_set) and (not c_clr)); -- set
end toggle;
function f_all_names return t_all_name_array is
......
modules/wr_softpll_ng/spll_bangbang_pd.vhd
View file @ 35a77c9f
......@@ -96,6 +96,7 @@ architecture rtl of spll_bangbang_pd is
-- phase detector input signals (after division)
signal pd_in_ref : std_logic;
signal pd_in_fbck : std_logic;
signal r_pd_in_fbck : std_logic;
-- phase detector outputs
signal pd_a, pd_b, pd_t, pd_ta : std_logic;
......@@ -214,20 +215,20 @@ begin -- rtl
-- pd_in_ref <= clk_ref_div(0);
bb_pd_negedge : process(pd_in_fbck)
bb_pd_posnegedge : process(clk_fb_i)
begin
if falling_edge(pd_in_fbck) then
pd_ta <= pd_in_ref;
end if;
end process;
bb_pd_posedge : process(pd_in_fbck)
begin
if rising_edge(pd_in_fbck) then
pd_b <= pd_in_ref;
pd_a <= pd_b;
pd_t <= pd_ta;
if rising_edge(clk_fb_i) then
r_pd_in_fbck <= pd_in_fbck;
if r_pd_in_fbck = '1' and pd_in_fbck = '0' then -- falling edge
pd_ta <= pd_in_ref;
end if;
if r_pd_in_fbck = '0' and pd_in_fbck = '1' then -- rising_edge
pd_b <= pd_in_ref;
pd_a <= pd_b;
pd_t <= pd_ta;
end if;
end if;
end process;
......
platform/altera/altera_phase.vhd
View file @ 35a77c9f
......@@ -124,10 +124,10 @@ architecture rtl of altera_phase is
-- We ensure timing between these nodes via the state machine
attribute altera_attribute : string;
attribute altera_attribute OF rtl : architecture is
("-name SDC_STATEMENT ""set_false_path -from {altera_phase:*|prime_trap} -to {altera_phase:*|raw_trap}"";" &
"-name SDC_STATEMENT ""set_false_path -from {altera_phase:*|raw_trap} -to {altera_phase:*|sync_trap*}"";" &
"-name SDC_STATEMENT ""set_false_path -to {altera_phase:*|aligned*}"";" &
"-name SDC_STATEMENT ""set_false_path -from {altera_phase:*|gen_rstn*} -to {altera_phase:*|sync_rstn*}""");
("-name SDC_STATEMENT ""set_false_path -from {*|altera_phase:*|prime_trap} -to {*|altera_phase:*|raw_trap}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_phase:*|raw_trap} -to {*|altera_phase:*|sync_trap*}"";" &
"-name SDC_STATEMENT ""set_false_path -to {*|altera_phase:*|aligned*}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_phase:*|gen_rstn*} -to {*|altera_phase:*|sync_rstn*}""");
begin
-- Pulse width of phasedone_i can be less than clock period... so make a trap
......
platform/altera/altera_pkg.vhd
View file @ 35a77c9f
......@@ -74,8 +74,9 @@ package wr_altera_pkg is
areset : in std_logic;
inclk0 : in std_logic := '0'; -- 125 MHz
c0 : out std_logic; -- 62.5 MHz
c1 : out std_logic; -- 50 MHz
c2 : out std_logic; -- 20 MHz
c1 : out std_logic; -- 50 MHz (flash+reconfig)
c2 : out std_logic; -- 20 MHz (display+scubus)
c3 : out std_logic; -- 10 MHz (remote update)
locked : out std_logic);
end component;
......@@ -83,9 +84,9 @@ package wr_altera_pkg is
port(
refclk : in std_logic := 'X'; -- 125 MHz
outclk_0 : out std_logic; -- 62.5 MHz
outclk_1 : out std_logic; -- 20 MHz
outclk_2 : out std_logic; -- 100 MHz
outclk_3 : out std_logic; -- 100 MHz
outclk_1 : out std_logic; -- 100 MHz (flash+reconfig)
outclk_2 : out std_logic; -- 20 MHz (display+scubus)
outclk_3 : out std_logic; -- 10 MHz (remote update)
rst : in std_logic := 'X';
locked : out std_logic);
end component;
......
platform/altera/altera_reset.vhd
View file @ 35a77c9f
......@@ -91,8 +91,8 @@ architecture rtl of altera_reset is
-- We ensure timing between these nodes via the state machine
attribute altera_attribute : string;
attribute altera_attribute OF rtl : architecture is
("-name SDC_STATEMENT ""set_false_path -to {altera_reset:*|locked[2]}"";" &
"-name SDC_STATEMENT ""set_false_path -from {altera_reset:*|waiting} -to {altera_reset:*|nresets*}""");
("-name SDC_STATEMENT ""set_false_path -to {*|altera_reset:*|locked[2]}"";" &
"-name SDC_STATEMENT ""set_false_path -from {*|altera_reset:*|waiting} -to {*|altera_reset:*|nresets*}""");
begin
......
platform/altera/arria2_pll/sys_pll.txt
View file @ 35a77c9f
......@@ -100,12 +100,14 @@
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
......@@ -122,6 +124,10 @@
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
......
platform/altera/arria5_pll/sys_pll5.txt
View file @ 35a77c9f
......@@ -23,7 +23,7 @@
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="20.0" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
......@@ -31,7 +31,7 @@
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="20.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
......@@ -39,7 +39,7 @@
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="10.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
......
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