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White Rabbit core collection
Commit d7453e86 authored by Tristan Gingold's avatar Tristan Gingold
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board/common: re-allow streamer and etherbone

parent aca968bc
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    board/common/xwrc_board_common.vhd
    View file @ d7453e86
    ...@@ -496,86 +496,86 @@ begin -- architecture struct ...@@ -496,86 +496,86 @@ begin -- architecture struct
    gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate gen_wr_streamers : if (g_fabric_iface = STREAMERS) generate
    --GD cmp_xwr_streamers : xwr_streamers cmp_xwr_streamers : xwr_streamers
    --GD generic map ( generic map (
    --GD g_streamers_op_mode => g_streamers_op_mode, g_streamers_op_mode => g_streamers_op_mode,
    --GD g_tx_streamer_params => g_tx_streamer_params, g_tx_streamer_params => g_tx_streamer_params,
    --GD g_rx_streamer_params => g_rx_streamer_params, g_rx_streamer_params => g_rx_streamer_params,
    --GD g_simulation => g_simulation, g_simulation => g_simulation,
    --GD g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit)) g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
    --GD port map ( port map (
    --GD clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
    --GD rst_n_i => rst_n_i, rst_n_i => rst_n_i,
    --GD src_i => wrf_snk_out, src_i => wrf_snk_out,
    --GD src_o => wrf_snk_in, src_o => wrf_snk_in,
    --GD snk_i => wrf_src_out, snk_i => wrf_src_out,
    --GD snk_o => wrf_src_in, snk_o => wrf_src_in,
    --GD tx_data_i => wrs_tx_data_i, tx_data_i => wrs_tx_data_i,
    --GD tx_valid_i => wrs_tx_valid_i, tx_valid_i => wrs_tx_valid_i,
    --GD tx_dreq_o => wrs_tx_dreq_o, tx_dreq_o => wrs_tx_dreq_o,
    --GD tx_last_p1_i => wrs_tx_last_i, tx_last_p1_i => wrs_tx_last_i,
    --GD tx_flush_p1_i => wrs_tx_flush_i, tx_flush_p1_i => wrs_tx_flush_i,
    --GD rx_first_p1_o => wrs_rx_first_o, rx_first_p1_o => wrs_rx_first_o,
    --GD rx_last_p1_o => wrs_rx_last_o, rx_last_p1_o => wrs_rx_last_o,
    --GD rx_data_o => wrs_rx_data_o, rx_data_o => wrs_rx_data_o,
    --GD rx_valid_o => wrs_rx_valid_o, rx_valid_o => wrs_rx_valid_o,
    --GD rx_dreq_i => wrs_rx_dreq_i, rx_dreq_i => wrs_rx_dreq_i,
    --GD clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
    --GD tm_time_valid_i => tm_time_valid, tm_time_valid_i => tm_time_valid,
    --GD tm_tai_i => tm_tai, tm_tai_i => tm_tai,
    --GD tm_cycles_i => tm_cycles, tm_cycles_i => tm_cycles,
    --GD link_ok_i => link_ok, link_ok_i => link_ok,
    --GD wb_slave_i => aux_master_out, wb_slave_i => aux_master_out,
    --GD wb_slave_o => aux_master_in, wb_slave_o => aux_master_in,
    --GD snmp_array_o => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0), snmp_array_o => aux_diag_in(c_WR_STREAMERS_ARR_SIZE_OUT-1 downto 0),
    --GD snmp_array_i => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0), snmp_array_i => aux_diag_out(c_WR_STREAMERS_ARR_SIZE_IN-1 downto 0),
    --GD tx_streamer_cfg_i=> wrs_tx_cfg_i, tx_streamer_cfg_i=> wrs_tx_cfg_i,
    --GD rx_streamer_cfg_i=> wrs_rx_cfg_i); rx_streamer_cfg_i=> wrs_rx_cfg_i);
    --GD
    --GD -- unused output ports -- unused output ports
    --GD wrf_src_o <= c_dummy_snk_in; wrf_src_o <= c_dummy_snk_in;
    --GD wrf_snk_o <= c_dummy_src_in; wrf_snk_o <= c_dummy_src_in;
    --GD
    --GD aux_master_o <= cc_dummy_master_out; aux_master_o <= cc_dummy_master_out;
    --GD wb_eth_master_o <= cc_dummy_master_out; wb_eth_master_o <= cc_dummy_master_out;
    --GD
    --GD aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i; aux_diag_in(c_diag_ro_size-1 downto c_WR_STREAMERS_ARR_SIZE_OUT) <= aux_diag_i;
    --GD aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN); aux_diag_o <= aux_diag_out(c_diag_rw_size-1 downto c_WR_STREAMERS_ARR_SIZE_IN);
    end generate gen_wr_streamers; end generate gen_wr_streamers;
    gen_etherbone : if (g_fabric_iface = ETHERBONE) generate gen_etherbone : if (g_fabric_iface = ETHERBONE) generate
    --GD cmp_eb_ethernet_slave : eb_ethernet_slave cmp_eb_ethernet_slave : eb_ethernet_slave
    --GD generic map ( generic map (
    --GD g_sdb_address => x"0000000000030000") g_sdb_address => x"0000000000030000")
    --GD port map ( port map (
    --GD clk_i => clk_sys_i, clk_i => clk_sys_i,
    --GD nRst_i => aux_rst_n, nRst_i => aux_rst_n,
    --GD src_o => wrf_snk_in, src_o => wrf_snk_in,
    --GD src_i => wrf_snk_out, src_i => wrf_snk_out,
    --GD snk_o => wrf_src_in, snk_o => wrf_src_in,
    --GD snk_i => wrf_src_out, snk_i => wrf_src_out,
    --GD cfg_slave_o => aux_master_in, cfg_slave_o => aux_master_in,
    --GD cfg_slave_i => aux_master_out, cfg_slave_i => aux_master_out,
    --GD master_o => wb_eth_master_o, master_o => wb_eth_master_o,
    --GD master_i => wb_eth_master_i); master_i => wb_eth_master_i);
    --GD
    --GD -- unused output ports -- unused output ports
    --GD wrf_src_o <= c_dummy_snk_in; wrf_src_o <= c_dummy_snk_in;
    --GD wrf_snk_o <= c_dummy_src_in; wrf_snk_o <= c_dummy_src_in;
    --GD
    --GD wrs_tx_dreq_o <= '0'; wrs_tx_dreq_o <= '0';
    --GD wrs_rx_first_o <= '0'; wrs_rx_first_o <= '0';
    --GD wrs_rx_last_o <= '0'; wrs_rx_last_o <= '0';
    --GD wrs_rx_valid_o <= '0'; wrs_rx_valid_o <= '0';
    --GD wrs_rx_data_o <= (others => '0'); wrs_rx_data_o <= (others => '0');
    --GD
    --GD aux_master_o <= cc_dummy_master_out; aux_master_o <= cc_dummy_master_out;
    --GD
    --GD -- unused inputs to WR PTP core -- unused inputs to WR PTP core
    --GD aux_diag_in <= aux_diag_i; aux_diag_in <= aux_diag_i;
    --GD aux_diag_o <= aux_diag_out; aux_diag_o <= aux_diag_out;
    end generate gen_etherbone; end generate gen_etherbone;
    ......
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