[VXS support] bugfix in VXS board support

I prepared it based on SPEC's board support, I forgot to update vxs package name

[VXS support] bugfix in VXS board support
I prepared it based on SPEC's board support, I forgot to update vxs package name
d6c20bbf · Maciej Lipinski · 9b302f9c · d6c20bbf · d6c20bbf · d6c20bbf
Commit d6c20bbf authored Sep 07, 2018 by Maciej Lipinski
4 changed files
--- a/board/vxs/wr_vxs_pkg.vhd
+++ b/board/vxs/wr_vxs_pkg.vhd
@@ -3,11 +3,11 @@
 -- Project    : WR PTP Core
 -- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
 -------------------------------------------------------------------------------
-- File       : wrc_board_spec.vhd
+-- File       : wrc_board_vxs.vhd
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SPEC board.
+-- needed to operate the core on the VXS board.
-- http://www.ohwr.org/projects/spec/
+-- http://www.ohwr.org/projects/vxs/
 -------------------------------------------------------------------------------
 -- Copyright (c) 2018 CERN
 -------------------------------------------------------------------------------
@@ -41,7 +41,7 @@ use work.endpoint_pkg.all;
 use work.wr_board_pkg.all;
 use work.streamers_pkg.all;
-package wr_spec_pkg is
+package wr_vxs_pkg is
  component xwrc_board_vxs is
    generic (
@@ -310,4 +310,4 @@ package wr_spec_pkg is
      link_ok_o            : out std_logic);
  end component wrc_board_vxs;
-end wr_spec_pkg;
+end wr_vxs_pkg;
--- a/board/vxs/wrc_board_vxs.vhd
+++ b/board/vxs/wrc_board_vxs.vhd
@@ -6,10 +6,10 @@
 -- File       : wrc_board_vxs.vhd
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SPEC board.
+-- needed to operate the core on the VXS board.
 -- Version with no VHDL records on the top-level (mainly for Verilog
 -- instantiation).
-- http://www.ohwr.org/projects/spec/
+-- http://www.ohwr.org/projects/vxs/
 -------------------------------------------------------------------------------
 -- Copyright (c) 2018 CERN
 -------------------------------------------------------------------------------
@@ -46,7 +46,7 @@ use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_xilinx_pkg.all;
 use work.wr_board_pkg.all;
-use work.wr_spec_pkg.all;
+use work.wr_vxs_pkg.all;
 entity wrc_board_vxs is
  generic(

--- a/board/vxs/xwrc_board_vxs.vhd
+++ b/board/vxs/xwrc_board_vxs.vhd
@@ -3,11 +3,11 @@
 -- Project    : WR PTP Core
 -- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
 -------------------------------------------------------------------------------
-- File       : xwrc_board_spec.vhd
+-- File       : xwrc_board_vxs.vhd
 -------------------------------------------------------------------------------
 -- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the SPEC board.
+-- needed to operate the core on the VXS board.
-- http://www.ohwr.org/projects/spec/
+-- http://www.ohwr.org/projects/vxs/
 -------------------------------------------------------------------------------
 -- Copyright (c) 2018 CERN
 -------------------------------------------------------------------------------
@@ -44,7 +44,7 @@ use work.endpoint_pkg.all;
 use work.streamers_pkg.all;
 use work.wr_xilinx_pkg.all;
 use work.wr_board_pkg.all;
-use work.wr_spec_pkg.all;
+use work.wr_vxs_pkg.all;
 library unisim;
 use unisim.vcomponents.all;

--- a/top/vxs_ref_design/vxs_wr_ref_top.vhd
+++ b/top/vxs_ref_design/vxs_wr_ref_top.vhd
@@ -39,7 +39,7 @@ library work;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
 use work.wr_board_pkg.all;
-use work.wr_spec_pkg.all;
+use work.wr_vxs_pkg.all;
 use work.gn4124_core_pkg.all;
 library unisim;