[tb/wrpc] a major remake of the testbench, see main.sv description

for details how it works now.

Short description of changes
- frames are generated in two places: LM32 and main.sv
- frames from LM32 are looped back in main.sv
- frames from main.sv go through WRPC and are looped back by wrf_loopback
- frames generated by main.sv have randome size, Inter-frame gap
  is randome for one bunch of sent frames, and fixed low for stress
  in another bunch of sent frames.
- frames from LM32 are sent as fast as possible, which is sloooow
- frames from LM32 have codes to indicate to the simulation problems
  of reception of previous frame (no other easy way for information
  to pass from LM32 to main.sv
- all frames have seqID which is verified in main.sv
- warnings are thrown when
  * wrong seqID is detected by main.sv
  * when ERROR code is sent by LM32, can be on seqID mismatch, or
    rx function error

NOTE: the software for LM32 is now compiled by proper make config
in wrpc-sw (see wrpc-sw/config): wrpc_sim_defconfig