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White Rabbit core collection
Commit cd942e13 authored by Andela Kostic's avatar Andela Kostic
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Support both wrc_core and streamers-on-spec_trigger-distribution testbenches 

Now, in testbench/wrc_core there are two folders - modelsim and riviera. Each of them contains
Manifest.py and run.do adjusted for the simulation with ModelSim/Riviera. One should navigate to
one of these folders to run the simulation with the corresponding simulator.

The streamers-on-spec_trigger-distribution testbench works now for wrpc-v5 in ModelSim.
However, it does not work with Riviera. The problem is that the secureip library cannot be
compiled for the spartan 6 and the Riviera version after 2008.
parent db46b00a
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    Showing with 216 additions and 36 deletions
    board/spec/xwrc_board_spec.vhd
    View file @ cd942e13
    ......@@ -73,6 +73,7 @@ entity xwrc_board_spec is
    g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
    -- memory initialisation file for embedded CPU
    g_dpram_initf : string := "default_xilinx";
    g_dpram_size : integer := 144*1024/4;
    -- identification (id and ver) of the layout of words in the generic diag interface
    g_diag_id : integer := 0;
    g_diag_ver : integer := 0;
    ......@@ -449,7 +450,7 @@ begin -- architecture struct
    g_ep_rxbuf_size => 1024,
    g_tx_runt_padding => TRUE,
    g_dpram_initf => g_dpram_initf,
    g_dpram_size => 144*1024/4,
    g_dpram_size => g_dpram_size,
    g_interface_mode => PIPELINED,
    g_address_granularity => BYTE,
    g_aux_sdb => g_aux_sdb,
    ......
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/Manifest.py
    View file @ cd942e13
    action= "simulation"
    target= "xilinx"
    syn_device="xc6slx45t"
    #sim_tool="modelsim"
    sim_tool="riviera"
    top_module="main"
    fetchto="../../ip_cores"
    vlog_opt="+incdir+../../../sim +incdir"
    vcom_opt="-relax -packagevhdlsv"
    include_dirs = ["../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src" ]
    modules = { "local" : ["../../..",
    ......@@ -16,6 +8,6 @@ modules = { "local" : ["../../..",
    "../../../ip_cores/general-cores",
    "../../../ip_cores/urv-core"]}
    files = ["main.sv","synthesis_descriptor.vhd"]
    files = ["synthesis_descriptor.vhd"]
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/modelsim/Manifest.py 0 → 100644
    View file @ cd942e13
    action= "simulation"
    target= "xilinx"
    syn_device="xc6slx45t"
    sim_tool="modelsim"
    top_module="main"
    vcom_opt="-mixedsvvh"
    include_dirs = [ "../" ]
    modules = {
    "local" : [ "../" ]
    }
    files = [ "main.sv" ]
    \ No newline at end of file
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/modelsim/main.sv 0 → 100644
    View file @ cd942e13
    //
    // White Rabbit Core Hands-On Course
    //
    // Lesson 04a: Trivial streamer demo
    //
    // Objectives:
    // - Demonstrate pulse distribution example on a simulation
    //
    // Brief description:
    // Testbench instantiates two SPEC cards connected to each other via a Gigabit
    // Ethernet link. SPEC A sends input trigger pulses to SPEC B, which reproduces them with
    // fixed, 20us delay.
    `timescale 10fs/10fs // need very fine timestep to correctly simulate the GTP.
    module main;
    // Parameters
    // Reference clock period.
    parameter g_ref_clock_period = 8ns;
    reg clk_20m = 0, clk_ref = 0;
    wire uart_txd;
    wire [7:0] uart_data;
    wire uart_data_valid;
    // Generate the reference clock
    always #(g_ref_clock_period / 2) clk_ref <= ~clk_ref;
    // Generate the 20 MHz VCXO clock
    always #(50ns / 2) clk_20m <= ~clk_20m;
    reg pulse_in = 0;
    wire pulse_out;
    wire [4:0] dio_out_b;
    // This time we have two SPECs talking to each other in the same testbench
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_A (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    .clk_125m_gtp_p_i (clk_ref),
    .clk_125m_gtp_n_i (~clk_ref),
    .clk_20m_vcxo_i(clk_20m),
    // Connect the gigabit output of one SPEC with the RX input of the other,
    // and vice-versa.
    .sfp_txp_o(a_to_b_p),
    .sfp_txn_o(a_to_b_n),
    .sfp_rxp_i(b_to_a_p),
    .sfp_rxn_i(b_to_a_n),
    .dio_p_i( {3'b0, pulse_in, 1'b0} ),
    .dio_n_i( {3'b1, ~pulse_in, 1'b1} )
    );
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_B (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    .clk_125m_gtp_p_i (clk_ref),
    .clk_125m_gtp_n_i (~clk_ref),
    .clk_20m_vcxo_i(clk_20m),
    // Connect the gigabit output of one SPEC with the RX input of the other,
    // and vice-versa.
    .sfp_txp_o(b_to_a_p),
    .sfp_txn_o(b_to_a_n),
    .sfp_rxp_i(a_to_b_p),
    .sfp_rxn_i(a_to_b_n),
    .dio_p_o ( dio_out_b )
    );
    assign pulse_out = dio_out_b[2];
    // observe the link LEDs on both sides, and tell us when the link is ready.
    wire link_up_a = SPEC_A.cmp_xwrc_board_spec.led_link_o;
    wire link_up_b = SPEC_B.cmp_xwrc_board_spec.led_link_o;
    initial begin
    // wait until both SPECs see the Ethernet link. Otherwise the packet we're going
    // to send might end up in void...
    $display("Start very looooong wait until link is OK (over 600us)");
    #520us
    wait(link_up_a == 1'b1 && link_up_b == 1'b1);
    #10us
    $display("Stop very looooong wait until link is OK");
    forever begin // send a pulse every 30 us;
    pulse_in = 1;
    #1us;
    pulse_in = 0;
    #30us;
    end
    end
    endmodule // main
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/run.do → testbench/wr_streamers/streamers-on-spec_trigger-distribution/modelsim/run.do
    View file @ cd942e13
    # make -f Makefile > /dev/null 2>&1
    # Modelsim run script
    vsim -L unisim -L secureip work.main -voptargs="+acc"
    set NumericStdNoWarnings 1
    set StdArithNoWarnings 1
    do wave.do
    do ../wave.do
    run 40000us
    wave zoomfull
    radix -hex
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/riviera/Manifest.py 0 → 100644
    View file @ cd942e13
    action= "simulation"
    target= "xilinx"
    syn_device="xc6slx45t"
    sim_tool="riviera"
    top_module="main"
    vcom_opt="-relax -packagevhdlsv"
    include_dirs = [ "../" ]
    modules = {
    "local" : [ "../" ]
    }
    files = [ "main.sv" ]
    \ No newline at end of file
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv → testbench/wr_streamers/streamers-on-spec_trigger-distribution/riviera/main.sv
    View file @ cd942e13
    ......@@ -35,13 +35,12 @@ module main;
    wire pulse_out;
    wire [4:0] dio_out_b;
    // This time we have two SPECs talking to each other in the same testbench
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_A (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    ......@@ -66,7 +65,8 @@ module main;
    spec_top
    #(
    .g_simulation (1),
    .g_dpram_initf("../../../bin/wrpc/wrc_phy8_sim.bram")
    .g_dpram_initf("../../../../bin/wrpc/wrc.bram"),
    .g_dpram_size(196608/4)
    ) SPEC_B (
    .clk_125m_pllref_p_i (clk_ref),
    .clk_125m_pllref_n_i (~clk_ref),
    ......@@ -91,8 +91,8 @@ module main;
    // observe the link LEDs on both sides, and tell us when the link is ready.
    wire link_up_a = $signal_agent("SPEC_A.cmp_xwrc_board_spec.led_link_o","led_link_o",1);
    wire link_up_b = $signal_agent("SPEC_B.cmp_xwrc_board_spec.led_link_o","lend_link_o",1);
    wire link_up_a = $signal_agent("SPEC_A.cmp_xwrc_board_spec.led_link_o","link_up_a",1);
    wire link_up_b = $signal_agent("SPEC_B.cmp_xwrc_board_spec.led_link_o","link_up_b",1);
    initial begin
    // wait until both SPECs see the Ethernet link. Otherwise the packet we're going
    ......
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/riviera/run.do 0 → 100644
    View file @ cd942e13
    # Riviera run script
    vsim -L unisim -L secureip work.main +access +r +access +w_nets -ieee_nowarn
    do ../wave_ci.do
    run 40000us
    wave zoomfull
    radix -hexadecimal
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave.do
    View file @ cd942e13
    ......@@ -33,6 +33,7 @@ add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board
    add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_k
    add wave -noupdate -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_enc_err
    add wave -noupdate -divider {SPEC B - WR timing}
    add wave -noupdate -radix hexadecimal /main/SPEC_B/dio_p_o(2)
    add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_time_valid_i
    add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_tai_i
    add wave -noupdate /main/SPEC_B/U_Pulse_Stamper/tm_cycles_i
    ......
    testbench/wr_streamers/streamers-on-spec_trigger-distribution/wave_ci.do
    View file @ cd942e13
    ......@@ -33,6 +33,7 @@ add wave -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/p
    add wave -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_o.tx_k
    add wave -radix hexadecimal /main/SPEC_B/cmp_xwrc_board_spec/cmp_board_common/phy8_i.tx_enc_err
    add wave -divider {SPEC B - WR timing}
    add wave -radix hexadecimal /main/SPEC_B/dio_p_o(2)
    add wave /main/SPEC_B/U_Pulse_Stamper/tm_time_valid_i
    add wave /main/SPEC_B/U_Pulse_Stamper/tm_tai_i
    add wave /main/SPEC_B/U_Pulse_Stamper/tm_cycles_i
    ......
    testbench/wrc_core/Manifest.py
    View file @ cd942e13
    action = "simulation"
    target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    #sim_tool = "modelsim"
    sim_tool = "riviera"
    top_module = "main"
    fetchto = "../../ip_cores"
    vlog_opt = "+incdir+../../sim"
    # comment out the next line for ModelSim
    #vcom_opt="-mixedsvvh"
    files = [ "main.sv" ]
    include_dirs = [ "../../sim",
    ......@@ -25,4 +14,3 @@ modules = { "local" : [ "../../",
    "../../ip_cores/gn4124-core" ]}
    testbench/wrc_core/main.sv
    View file @ cd942e13
    ......@@ -160,7 +160,7 @@ module main;
    wire wrc_snk_stall;
    wire wrc_snk_err;
    wire link_up;
    // globa variables for "tiemout" in case the transmitted frames are not received
    // globa variables for "timeout" in case the transmitted frames are not received
    int rx_sth = 0;
    int tx_sth = 0;
    int wait_cnt = 0;
    ......@@ -173,7 +173,7 @@ module main;
    .g_address_granularity (BYTE),
    .g_tx_runt_padding (1),
    .g_with_external_clock_input(1),
    .g_dpram_initf ("../../bin/wrpc/wrc.bram"),
    .g_dpram_initf ("../../../bin/wrpc/wrc.bram"),
    .g_dpram_size (196608/4),
    .g_diag_id (1),
    .g_diag_ver (2),
    ......
    testbench/wrc_core/modelsim/Manifest.py 0 → 100644
    View file @ cd942e13
    action = "simulation"
    target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    top_module = "main"
    sim_tool = "modelsim"
    vcom_opt="-mixedsvvh"
    include_dirs = [ "../../../sim",
    "../" ]
    modules = {
    "local" : [ "../" ]
    }
    \ No newline at end of file
    testbench/wrc_core/run.do → testbench/wrc_core/modelsim/run.do
    View file @ cd942e13
    ......@@ -3,7 +3,7 @@
    vsim -L unisim -t 10fs work.main -voptargs="+acc"
    set StdArithNoWarnings 1
    set NumericStdNoWarnings 1
    do wave.do
    do ../wave.do
    radix -hexadecimal
    run 200ms
    wave zoomfull
    ......
    testbench/wrc_core/riviera/Manifest.py 0 → 100644
    View file @ cd942e13
    action = "simulation"
    target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    top_module = "main"
    sim_tool = "riviera"
    vcom_opt="-relax -packagevhdlsv"
    fetchto = "../../../ip_cores"
    vlog_opt = "+incdir+../../sim"
    include_dirs = [ "../../../sim",
    "../" ]
    modules = {
    "local" : [ "../" ]
    }
    \ No newline at end of file
    testbench/wrc_core/run_riv.do → testbench/wrc_core/riviera/run.do
    View file @ cd942e13
    # Riviera run script
    # execute: vsim -c -do "run_riv.do"
    # execute: vsim -c -do "run.do"
    vsim -L unisim -t 10fs work.main +access +r -ieee_nowarn
    # for ModelSim (for Riviera this is already done with -ieee_nowarn)
    #set StdArithNoWarnings 1
    #set NumericStdNoWarnings 1
    do wave_ci.do
    do ../wave_ci.do
    radix -hexadecimal
    run 200ms
    wave zoomfull
    ......
    top/spec_1_1/wr_streamers_demo/spec_top.vhd
    View file @ cd942e13
    ......@@ -80,7 +80,8 @@ entity spec_top is
    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
    g_simulation : integer := 0
    g_simulation : integer := 0;
    g_dpram_size : integer := (144*1024/4)
    );
    port (
    ---------------------------------------------------------------------------
    ......@@ -260,7 +261,7 @@ architecture top of spec_top is
    -----------------------------------------------------------------------------
    -- Trigger-to-output value, in 8 ns ticks. Set by default to 20us to work
    -- for 10km+ fibers.
    constant c_PULSE_DELAY : integer := 30000/8;
    constant c_PULSE_DELAY : integer := 20000/8;
    constant tx_streamer_params : t_tx_streamer_params := (
    -- We send each timestamp (40 TAI bits + 28
    ......@@ -443,11 +444,12 @@ begin -- architecture top
    -- The WR PTP core board package
    -----------------------------------------------------------------------------
    cmp_xwrc_board_spec : xwrc_board_spec
    cmp_xwrc_board_spec : entity work.xwrc_board_spec
    generic map (
    g_simulation => g_simulation,
    g_with_external_clock_input => TRUE,
    g_dpram_initf => g_dpram_initf,
    g_dpram_size => g_dpram_size,
    g_fabric_iface => STREAMERS,
    g_tx_streamer_params => tx_streamer_params,
    g_rx_streamer_params => rx_streamer_params)
    ......
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