Add generic: Artix7 gtp depends on rx_byte_is_aligned

c2b7c093 · Peter Jansweijer · d7c7b52e · c2b7c093 · c2b7c093
Commit c2b7c093 authored Dec 11, 2023 by Peter Jansweijer
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Showing with 15 additions and 8 deletions

wr_gtp_phy_family7.vhd ...form/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd +4 -2

gtp_bitslide.vhd platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd +11 -6

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--- a/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
@@ -256,7 +256,8 @@ architecture structure of wr_gtp_phy_family7 is
  component gtp_bitslide is
  generic (
    g_simulation             :    integer;
-    g_target                 :    string := "artix7"
+    g_target                 :    string := "artix7";
+    g_use_rx_byte_is_aligned :    boolean := false
  );
  port (
    gtp_rst_i                : in  std_logic;
@@ -465,7 +466,8 @@ begin
  U_Bitslide : gtp_bitslide
  generic map (
    g_simulation             =>  g_simulation,
-    g_target                 =>  ("artix7")
+    g_target                 =>  ("artix7"),
+    g_use_rx_byte_is_aligned =>  true
  )
  port map (
    gtp_rst_i                =>  rst_done_n,

--- a/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2020-07-08
+-- Last update: 2023-12-11
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -39,6 +39,7 @@
 -- 2010-11-18  0.4      twlostow  Ported EASE design to VHDL 
 -- 2011-02-07  0.5      twlostow  Verified on Spartan6 GTP
 -- 2011-09-12  0.6      twlostow  Virtex6 port
+-- 2023-12-11  0.7      peterj    Artix7 gtp depends on rx_byte_is_aligned
 -------------------------------------------------------------------------------

 library ieee;
@@ -49,8 +50,9 @@ entity gtp_bitslide is
  
  generic (
 -- set to non-zero value to enable some simulation speedups (reduce delays)
-    g_simulation : integer;
-    g_target     : string := "spartan6");
+    g_simulation             : integer;
+    g_target                 : string  := "spartan6";
+    g_use_rx_byte_is_aligned : boolean := false);

  port (
    gtp_rst_i : in std_logic;
@@ -240,13 +242,16 @@ begin  -- behavioral
          else
            counter <= counter + 1;
          end if;
-          
-          -- gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0' or 
-          if(counter = f_eval_link_down_threshold) then
+
+          if(g_use_rx_byte_is_aligned = true and (gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0')) then
+            gtp_rx_cdr_rst_o <= '1';
+            state            <= S_SYNC_LOST;
+          elsif (g_use_rx_byte_is_aligned = false and counter = f_eval_link_down_threshold) then
            report "serdes: link down" severity error;
            gtp_rx_cdr_rst_o <= '1';
            state            <= S_SYNC_LOST;
          end if;
+
        when others => null;
      end case;
    end if;