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White Rabbit core collection
Commit b2edc7ba authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_minic: added structized wrapper + updated Manifest

parent 0f14c50b
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modules/wr_mini_nic/Manifest.py
View file @ b2edc7ba
files = [ "minic_packet_buffer.vhd",
"minic_wb_slave.vhd",
"minic_wbgen2_pkg.vhd",
"wr_mini_nic.vhd" ];
"minic_wb_slave.vhd",
"minic_wbgen2_pkg.vhd",
"wr_mini_nic.vhd",
"xwr_mini_nic.vhd" ];
modules/wr_mini_nic/xwr_mini_nic.vhd 0 → 100644
View file @ b2edc7ba
library ieee;
use ieee.std_logic_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
entity xwr_mini_nic is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_memsize_log2 : integer := 14;
g_buffer_little_endian : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- System memory i/f
-------------------------------------------------------------------------------
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
-------------------------------------------------------------------------------
-- Pipelined Wishbone interface
-------------------------------------------------------------------------------
-- WBP Master (TX)
src_o: out t_wrf_source_out;
src_i: in t_wrf_source_in;
-- WBP Slave (RX)
snk_o: out t_wrf_sink_out;
snk_i: in t_wrf_sink_in;
-------------------------------------------------------------------------------
-- TXTSU i/f
-------------------------------------------------------------------------------
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone slave
-------------------------------------------------------------------------------
wb_i: in t_wishbone_slave_in;
wb_o: out t_wishbone_slave_out
);
end xwr_mini_nic;
architecture wrapper of xwr_mini_nic is
component wr_mini_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_err_i : in std_logic;
src_ack_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_ack_o : out std_logic;
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic);
end component;
begin -- wrapper
wr_mini_nic_1: wr_mini_nic
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_memsize_log2 => g_memsize_log2,
g_buffer_little_endian => g_buffer_little_endian)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
mem_data_o => mem_data_o,
mem_addr_o => mem_addr_o,
mem_data_i => mem_data_i,
mem_wr_o => mem_wr_o,
src_dat_o => src_o.dat,
src_adr_o => src_o.adr,
src_sel_o => src_o.sel,
src_cyc_o => src_o.cyc,
src_stb_o => src_o.stb,
src_we_o => src_o.we,
src_stall_i => src_i.stall,
src_err_i => src_i.err,
src_ack_i => src_i.ack,
snk_dat_i => snk_i.dat,
snk_adr_i => snk_i.adr,
snk_sel_i => snk_i.sel,
snk_cyc_i => snk_i.cyc,
snk_stb_i => snk_i.stb,
snk_we_i => snk_i.we,
snk_stall_o => snk_o.stall,
snk_err_o => snk_o.err,
snk_ack_o => snk_o.ack,
txtsu_port_id_i => txtsu_port_id_i,
txtsu_frame_id_i => txtsu_frame_id_i,
txtsu_tsval_i => txtsu_tsval_i,
txtsu_valid_i => txtsu_valid_i,
txtsu_ack_o => txtsu_ack_o,
wb_cyc_i => wb_i.cyc,
wb_stb_i => wb_i.stb,
wb_we_i => wb_i.we,
wb_sel_i => wb_i.sel,
wb_adr_i => wb_i.adr,
wb_dat_i => wb_i.dat,
wb_dat_o => wb_o.dat,
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
wb_irq_o => wb_o.int);
end wrapper;
modules/wrc_core/Manifest.py 0 → 100644
View file @ b2edc7ba
files = [ "wr_core.vhd",
"wrc_dpram.vhd",
"wrcore_pkg.vhd",
"wrc_periph.vhd",
"wb_reset.vhd" ];
fetchto = "../../ip_cores"
modules/wrc_lm32/Manifest.py
View file @ b2edc7ba
......@@ -10,5 +10,8 @@ files = [ "wrc_lm32.vhd",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_interrupt.v",
"lm32_dp_ram.v"
"lm32_dp_ram.v",
"lm32_debug.v",
"lm32_jtag.v",
"jtag_wb.v"
];
\ No newline at end of file
modules/wrc_lm32/jtag_wb.v 0 → 100644
View file @ b2edc7ba
/* Added by GSI to support debug over wishbone */
`define ACK_DELAY 8 /* Give the JTAG core time to latch after a write */
module jtag_wb (
clk_i,
DAT_I,
ADR_I,
CYC_I,
SEL_I,
STB_I,
WE_I,
reg_d,
reg_addr_d,
ACK_O,
STALL_O,
DAT_O,
reg_update,
reg_q,
reg_addr_q,
jtck,
jrstn
);
input clk_i;
input [`LM32_WORD_RNG] DAT_I;
input [`LM32_WORD_RNG] ADR_I;
input CYC_I;
input [`LM32_BYTE_SELECT_RNG] SEL_I;
input STB_I;
input WE_I;
input [7:0] reg_d;
input [2:0] reg_addr_d;
output ACK_O;
output STALL_O;
output [`LM32_WORD_RNG] DAT_O;
output reg_update;
output [7:0] reg_q;
output [2:0] reg_addr_q;
output jtck;
output jrstn;
reg [7:0] reg_q;
reg [2:0] reg_addr_q;
reg [`ACK_DELAY-1:0] ack_shift;
assign reg_update = (CYC_I == `TRUE) &&
(STB_I == `TRUE) &&
(WE_I == `TRUE);
assign DAT_O[31:11] = 21'h0;
assign DAT_O[10:3] = reg_d;
assign DAT_O[2:0] = reg_addr_d;
assign jtck = clk_i;
assign jrstn = 1;
assign ACK_O = ack_shift[0];
assign STALL_O = |ack_shift[`ACK_DELAY-1:1];
always @(posedge clk_i)
begin
ack_shift <=
{CYC_I == `TRUE && STB_I == `TRUE && STALL_O == `FALSE,
ack_shift[`ACK_DELAY-1:1]};
if (reg_update == `TRUE)
begin
reg_q <= DAT_I[10:3];
reg_addr_q <= DAT_I[2:0];
end
end
endmodule
modules/wrc_lm32/lm32_interrupt.v
View file @ b2edc7ba
......@@ -182,7 +182,7 @@ begin
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
endcase
end
end
endgenerate
......@@ -191,72 +191,91 @@ endgenerate
// Sequential Logic
/////////////////////////////////////////////////////
`define IE_DELAY 10
reg [`IE_DELAY:0] eie_delay = 0;
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
if(eie_delay[0])
ie <= eie;
eie_delay <= {1'b0, eie_delay[`IE_DELAY:1]};
if (eret_q_x == `TRUE) begin
// Restore interrupt enable
ie <= eie;
eie_delay[`IE_DELAY] <= `TRUE;
eie_delay[`IE_DELAY-1:0] <= 0;
end
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
im <= csr_write_data[interrupts-1:0];
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
......@@ -266,64 +285,74 @@ else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
bie <= `FALSE;
`endif
ip <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
begin
if(eie_delay[0])
ie <= eie;
eie_delay <= {1'b0, eie_delay[`IE_DELAY:1]};
if (eret_q_x == `TRUE) begin
// Restore interrupt enable
ie <= eie;
eie_delay[`IE_DELAY] <= `TRUE;
eie_delay[`IE_DELAY-1:0] <= 0;
end
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
......
modules/wrc_lm32/lm32_top.v
View file @ b2edc7ba
......@@ -51,6 +51,14 @@ module lm32_top (
I_ACK_I,
I_ERR_I,
I_RTY_I,
`endif
`ifdef CFG_JWB_ENABLED
J_DAT_I,
J_ADR_I,
J_CYC_I,
J_SEL_I,
J_STB_I,
J_WE_I,
`endif
// Data Wishbone master
D_DAT_I,
......@@ -75,6 +83,10 @@ module lm32_top (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
`endif
`ifdef CFG_JWB_ENABLED
J_ACK_O,
J_DAT_O,
`endif
// Data Wishbone master
D_DAT_O,
......@@ -85,7 +97,10 @@ module lm32_top (
D_WE_O,
D_CTI_O,
D_LOCK_O,
D_BTE_O
D_BTE_O,
trace_pc_o,
trace_eret_o,
trace_pc_valid_o
);
/////////////////////////////////////////////////////
......@@ -111,6 +126,15 @@ input I_ERR_I; // Instruction Wishbone interfac
input I_RTY_I; // Instruction Wishbone interface retry
`endif
`ifdef CFG_JWB_ENABLED
input [`LM32_WORD_RNG] J_DAT_I;
input [`LM32_WORD_RNG] J_ADR_I;
input J_CYC_I;
input [`LM32_BYTE_SELECT_RNG] J_SEL_I;
input J_STB_I;
input J_WE_I;
`endif
input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
input D_ACK_I; // Data Wishbone interface acknowledgement
input D_ERR_I; // Data Wishbone interface error
......@@ -152,6 +176,13 @@ output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interfac
wire [`LM32_BTYPE_RNG] I_BTE_O;
`endif
`ifdef CFG_JWB_ENABLED
output J_ACK_O;
wire J_ACK_O;
output [`LM32_WORD_RNG] J_DAT_O;
wire [`LM32_WORD_RNG] J_DAT_O;
`endif
output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
wire [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
......@@ -199,6 +230,21 @@ wire trace_bret; // Indicates a bret instruction
`endif
`endif
output [31:0] trace_pc_o;
output trace_pc_valid_o;
output trace_eret_o;
`ifdef CFG_TRACE_ENABLED
assign trace_eret_o = trace_eret;
assign trace_pc_o =trace_pc;
assign trace_pc_valid_o = trace_pc_valid;
`else
assign trace_eret_o = 0;
assign trace_pc_o = 0;
assign trace_pc_valid_o = 0;
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
......@@ -276,7 +322,7 @@ lm32_cpu cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
`endif
`endif
// Data Wishbone master
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
......@@ -290,6 +336,29 @@ lm32_cpu cpu (
);
`ifdef CFG_JTAG_ENABLED
`ifdef CFG_JWB_ENABLED
jtag_wb jtag_wb (
// ----- Inputs -----
.clk_i (clk_i),
.DAT_I (J_DAT_I),
.ADR_I (J_ADR_I),
.CYC_I (J_CYC_I),
.SEL_I (J_SEL_I),
.STB_I (J_STB_I),
.WE_I (J_WE_I),
.reg_d (jtag_reg_d),
.reg_addr_d (jtag_reg_addr_d),
// ----- Outputs -----
.ACK_O (J_ACK_O),
.STALL_O (open),
.DAT_O (J_DAT_O),
.reg_update (jtag_update),
.reg_q (jtag_reg_q),
.reg_addr_q (jtag_reg_addr_q),
.jtck (jtck),
.jrstn (jrstn)
);
`else
// JTAG cores
jtag_cores jtag_cores (
// ----- Inputs -----
......@@ -302,6 +371,7 @@ jtag_cores jtag_cores (
.jtck (jtck),
.jrstn (jrstn)
);
`endif
`endif
`endif
endmodule
modules/wrc_lm32/system_conf.v
View file @ b2edc7ba
......@@ -36,12 +36,15 @@
//`define CFG_DCACHE_LIMIT 32'h7fffffff
// Enable Debugging
//`define CFG_JTAG_ENABLED
//`define CFG_JTAG_UART_ENABLED
//`define CFG_DEBUG_ENABLED
//`define CFG_HW_DEBUG_ENABLED
//`define CFG_BREAKPOINTS 32'h0
//`define CFG_WATCHPOINTS 32'h0
`define CFG_TRACE_ENABLED
`define CFG_JTAG_ENABLED
`define CFG_JTAG_UART_ENABLED
`define CFG_DEBUG_ENABLED
`define CFG_HW_DEBUG_ENABLED
`define CFG_BREAKPOINTS 32'h4
`define CFG_WATCHPOINTS 32'h4
`define CFG_JWB_ENABLED
`define CFG_INTERRUPTS_ENABLED
//`define CFG_BUS_ERRORS_ENABLED
......
modules/wrc_lm32/wrc_lm32.vhd
View file @ b2edc7ba
......@@ -18,6 +18,8 @@ entity wrc_lm32 is
iwb_dat_i : in std_logic_vector(31 downto 0);
iwb_cyc_o : out std_logic;
iwb_stb_o : out std_logic;
iwb_sel_o : out std_logic_vector(3 downto 0);
iwb_we_o : out std_logic;
iwb_ack_i : in std_logic;
dwb_adr_o : out std_logic_vector(g_addr_width-1 downto 0);
......@@ -27,7 +29,20 @@ entity wrc_lm32 is
dwb_stb_o : out std_logic;
dwb_sel_o : out std_logic_vector(3 downto 0);
dwb_we_o : out std_logic;
dwb_ack_i : in std_logic
dwb_ack_i : in std_logic;
jwb_adr_i : in std_logic_vector(g_addr_width-1 downto 0);
jwb_dat_i : in std_logic_vector(31 downto 0);
jwb_dat_o : out std_logic_vector(31 downto 0);
jwb_cyc_i : in std_logic;
jwb_stb_i : in std_logic;
jwb_sel_i : in std_logic_vector(3 downto 0);
jwb_we_i : in std_logic;
jwb_ack_o : out std_logic;
trace_pc_o: out std_logic_vector(31 downto 0);
trace_pc_valid_o: out std_logic;
trace_eret_o:out std_logic
);
end wrc_lm32;
......@@ -42,6 +57,12 @@ architecture rtl of wrc_lm32 is
I_ACK_I : in std_logic;
I_ERR_I : in std_logic;
I_RTY_I : in std_logic;
J_DAT_I : in std_logic_vector(31 downto 0);
J_ADR_I : in std_logic_vector(31 downto 0);
J_CYC_I : in std_logic;
J_SEL_I : in std_logic_vector(3 downto 0);
J_STB_I : in std_logic;
J_WE_I : in std_logic;
D_DAT_I : in std_logic_vector(31 downto 0);
D_ACK_I : in std_logic;
D_ERR_I : in std_logic;
......@@ -55,6 +76,8 @@ architecture rtl of wrc_lm32 is
I_CTI_O : out std_logic_vector(2 downto 0);
I_LOCK_O : out std_logic;
I_BTE_O : out std_logic_vector(1 downto 0);
J_ACK_O : out std_logic;
J_DAT_O : out std_logic_vector(31 downto 0);
D_DAT_O : out std_logic_vector(31 downto 0);
D_ADR_O : out std_logic_vector(31 downto 0);
D_CYC_O : out std_logic;
......@@ -63,16 +86,20 @@ architecture rtl of wrc_lm32 is
D_WE_O : out std_logic;
D_CTI_O : out std_logic_vector(2 downto 0);
D_LOCK_O : out std_logic;
D_BTE_O : out std_logic_vector(1 downto 0));
D_BTE_O : out std_logic_vector(1 downto 0);
trace_pc_o : out std_logic_vector(31 downto 0);
trace_pc_valid_o : out std_logic;
trace_eret_o: out std_logic);
end component lm32_top;
signal rst : std_logic;
signal iwb_adr_int : std_logic_vector(31 downto 0);
signal dwb_adr_int : std_logic_vector(31 downto 0);
signal jwb_adr_int : std_logic_vector(31 downto 0);
signal irqs_vec : std_logic_vector(31 downto 0);
signal dwb_data_int : std_logic_vector(31 downto 0);
begin
irqs_vec(g_num_irqs-1 downto 0) <= irq_i;
......@@ -90,6 +117,12 @@ begin
I_ACK_I => iwb_ack_i,
I_ERR_I => '0',
I_RTY_I => '0',
J_DAT_I => jwb_dat_i,
J_ADR_I => jwb_adr_int,
J_CYC_I => jwb_cyc_i,
J_SEL_I => jwb_sel_i,
J_STB_I => jwb_stb_i,
J_WE_I => jwb_we_i,
D_DAT_I => dwb_data_int,
D_ACK_I => dwb_ack_i,
D_ERR_I => '0',
......@@ -97,12 +130,14 @@ begin
I_DAT_O => iwb_dat_o,
I_ADR_O => iwb_adr_int,
I_CYC_O => iwb_cyc_o,
I_SEL_O => open,
I_SEL_O => iwb_sel_o,
I_STB_O => iwb_stb_o,
I_WE_O => open,
I_WE_O => iwb_we_o,
I_CTI_O => open,
I_LOCK_O => open,
I_BTE_O => open,
J_DAT_O => jwb_dat_o,
J_ACK_O => jwb_ack_o,
D_DAT_O => dwb_dat_o,
D_ADR_O => dwb_adr_int,
D_CYC_O => dwb_cyc_o,
......@@ -111,10 +146,17 @@ begin
D_WE_O => dwb_we_o,
D_CTI_O => open,
D_LOCK_O => open,
D_BTE_O => open);
D_BTE_O => open,
trace_pc_o => trace_pc_o,
trace_pc_valid_o => trace_pc_valid_o,
trace_eret_o => trace_eret_o);
iwb_adr_o <= iwb_adr_int(g_addr_width+1 downto 2);
dwb_adr_o <= dwb_adr_int(g_addr_width+1 downto 2);
jwb_adr_int(31 downto g_addr_width+2) <= (others => '0');
jwb_adr_int(g_addr_width+1 downto 2) <= jwb_adr_i;
jwb_adr_int(1 downto 0) <= (others => '0');
process(dwb_dat_i)
begin
......
platform/xilinx/chipscope/Manifest.py 0 → 100644
View file @ b2edc7ba
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
platform/xilinx/chipscope/chipscope_icon.ngc 0 → 100644
View file @ b2edc7ba
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
platform/xilinx/chipscope/chipscope_ila.ngc 0 → 100644
View file @ b2edc7ba
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec_1_1/wr_core_demo/Manifest.py 0 → 100644
View file @ b2edc7ba
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_top_wrc.xise"
modules = { "local" : [ "../../../top/spec_1_1/wr_core_demo", "../../../platform/xilinx/chipscope" ] }
testbench/wrc_core/main_tb/Manifest.py 0 → 100644
View file @ b2edc7ba
action = "simulation"
fetchto = "../../../ip_cores"
vlog_opt = "+incdir+../../../sim"
files = [ "main.sv", "wb_gpio_port_notristates.vhd" ]
modules = { "local" : "../../.." };
testbench/wrc_core/main_tb/main.sv 0 → 100644
View file @ b2edc7ba
`timescale 1ns/1ps
`include "if_wishbone.sv"
`include "endpoint_regs.v"
`include "endpoint_mdio.v"
`include "tbi_utils.sv"
`timescale 1ps/1ps
`define EP_QMODE_ACCESS 0
`define EP_QMODE_TRUNK 1
`define EP_QMODE_UNQ 3
// Clock periods (in picoseconds)
const int c_RBCLK_PERIOD = 8001;
const int c_REFCLK_PERIOD = 8000;
`define ADDR_RST_GEN 'h62000
module main;
wire clk_ref;
wire clk_sys;
wire rst_n;
IWishbone WB
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
tbi_clock_rst_gen
#(
.g_rbclk_period(8002))
clkgen(
.clk_ref_o(clk_ref),
.clk_sys_o(clk_sys),
.phy_rbclk_o(phy_rbclk),
.rst_n_o(rst_n)
);
wire clk_sys_dly;
assign #10 clk_sys_dly = clk_sys;
wire [7:0]phy_tx_data ;
wire phy_tx_k ;
wire phy_tx_disparity ;
wire phy_tx_enc_err ;
wire [7:0]phy_rx_data ;
wire phy_rx_rbclk ;
wire phy_rx_k ;
wire phy_rx_enc_err ;
wire [3:0]phy_rx_bitslide ;
wire phy_rst ;
wire phy_loopen;
wr_core #(
.g_simulation (1),
.g_virtual_uart(1),
.g_ep_rxbuf_size_log2 (12),
.g_dpram_initf ("/home/slayer/wrpc-sw/hello.ram"),
.g_dpram_size (16384),
.g_num_gpio (8)
)
DUT (
.clk_sys_i (clk_sys),
.clk_dmtd_i (clk_ref),
.clk_ref_i (clk_ref),
.rst_n_i (rst_n),
.pps_p_o (),
.dac_hpll_load_p1_o (),
.dac_hpll_data_o (),
.dac_dpll_load_p1_o (),
.dac_dpll_data_o (),
.gpio_o (),
.uart_rxd_i (1'b0),
.uart_txd_o (),
.wb_addr_i (WB.adr[17:0]),
.wb_data_i (WB.dat_o),
.wb_data_o (WB.dat_i),
.wb_sel_i (4'b1111),
.wb_we_i (WB.we),
.wb_cyc_i (WB.cyc),
.wb_stb_i (WB.stb),
.wb_ack_o (WB.ack),
.phy_ref_clk_i(clk_ref),
.phy_tx_data_o(phy_tx_data),
.phy_tx_k_o(phy_tx_k),
.phy_tx_disparity_i(phy_tx_disparity),
.phy_tx_enc_err_i(phy_tx_enc_err),
.phy_rx_data_i(phy_rx_data),
.phy_rx_rbclk_i(phy_rx_rbclk),
.phy_rx_k_i(phy_rx_k),
.phy_rx_enc_err_i(phy_rx_enc_err),
.phy_rx_bitslide_i(phy_rx_bitslide),
.phy_rst_o(phy_rst),
.phy_loopen_o(phy_lo),
.genrest_n ()
);
wr_gtp_phy_spartan6
#(
.g_simulation(1),
.g_ch0_use_refclk_out (0),
.g_ch1_use_refclk_out (0)
) PHY
(
.ch0_ref_clk_i(clk_ref),
.ch0_ref_clk_o(),
.ch0_tx_data_i(8'h00),
.ch0_tx_k_i(1'b0),
.ch0_tx_disparity_o(),
.ch0_tx_enc_err_o(),
.ch0_rx_rbclk_o(),
.ch0_rx_data_o(),
.ch0_rx_k_o(),
.ch0_rx_enc_err_o(),
.ch0_rx_bitslide_o(),
.ch0_rst_i(1'b0),
.ch0_loopen_i(1'b0),
.ch1_ref_clk_i(clk_ref),
.ch1_ref_clk_o(),
.ch1_tx_data_i(phy_tx_data),
.ch1_tx_k_i(phy_tx_k),
.ch1_tx_disparity_o(phy_tx_disparity),
.ch1_tx_enc_err_o(phy_tx_enc_err),
.ch1_rx_data_o(phy_rx_data),
.ch1_rx_rbclk_o(phy_rx_rbclk),
.ch1_rx_k_o(phy_rx_k),
.ch1_rx_enc_err_o(phy_rx_enc_err),
.ch1_rx_bitslide_o(phy_rx_bitslide),
.ch1_rst_i(phy_rst),
.ch1_loopen_i(phy_lo),
.pad_txn0_o(),
.pad_txp0_o(),
.pad_rxn0_i(1'b0),
.pad_rxp0_i(1'b0),
.pad_txn1_o(sfp_txn_o),
.pad_txp1_o(sfp_txp_o),
.pad_rxn1_i(sfp_rxn_i),
.pad_rxp1_i(sfp_rxp_i));
assign sfp_rxp_i = sfp_txp_o;
assign sfp_rxn_i = sfp_txn_o;
initial begin
@(posedge rst_n);
repeat(3) @(posedge clk_sys);
WB.write32('h40000, 1);
WB.write32('h40010, 'hdead);
forever begin
reg[31:0] rval;
repeat(100) @(posedge clk_sys);
WB.read32('h40000, rval);
if(rval[3]) begin
WB.read32('h40004, rval);
$display("Got TAG: %d", rval);
end
end
end
endmodule // main
top/spec_1_1/wr_core_demo/Manifest.py 0 → 100644
View file @ b2edc7ba
files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "wb_gpio_port_notristates.vhd"]
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../../"],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
}
top/spec_1_1/wr_core_demo/spec_serial_dac.vhd 0 → 100644
View file @ b2edc7ba
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spec_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8;
g_num_cs_select : integer := 2
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic
);
end spec_serial_dac;
architecture syn of spec_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
begin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(1); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(2); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(3); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(4); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(5); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(6); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(7); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(8); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_reg <= cs_sel_i;
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
gen_cs_out : for i in 0 to g_num_cs_select-1 generate
dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
end generate gen_cs_out;
dac_sclk_o <= iDacClk;
end syn;
top/spec_1_1/wr_core_demo/spec_serial_dac_arb.vhd 0 → 100644
View file @ b2edc7ba
library ieee;
use ieee.std_logic_1164.all;
entity spec_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end spec_serial_dac_arb;
architecture behavioral of spec_serial_dac_arb is
component spec_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer;
g_num_cs_select : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
U_DAC : spec_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits,
g_num_cs_select => 2)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cs_sel_i => dac_cs_sel,
load_i => dac_load,
sclk_divsel_i => "001",
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
dac_cs_sel <= (others => '0');
state <= WAIT_DATA;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when WAIT_DATA =>
if(d1_ready = '1') then
dac_cs_sel <= "01";
dac_data <= d1;
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_cs_sel <= "10";
dac_data <= d2;
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
top/spec_1_1/wr_core_demo/spec_top.ucf 0 → 100644
View file @ b2edc7ba
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "THERMO_ID" LOC = D4;
#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_b" LOC = F17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = C17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxn_i" LOC= C15;
#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
NET "sfp_txn_o" LOC= A16;
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
NET "FPGA_SCL_B" LOC = F7;
NET "FPGA_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FPGA_SDA_B" LOC = F8;
NET "FPGA_SDA_B" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
#NET "LA00_N" LOC = AB11;
#NET "LA00_N" IOSTANDARD = "LVCMOS25";
#NET "LA00_P" LOC = Y11;
#NET "LA00_P" IOSTANDARD = "LVCMOS25";
#NET "LA01_N" LOC = AB12;
#NET "LA01_N" IOSTANDARD = "LVCMOS25";
#NET "LA01_P" LOC = AA12;
#NET "LA01_P" IOSTANDARD = "LVCMOS25";
#NET "sda1_b" LOC = Y6;
#NET "sda1_b" IOSTANDARD = "LVCMOS25";
#NET "scl1_b" LOC = W6;
#NET "scl1_b" IOSTANDARD = "LVCMOS25";
#NET "LA02_N" LOC = Y6;
#NET "LA02_N" IOSTANDARD = "LVCMOS25";
#NET "LA02_P" LOC = W6;
#NET "LA02_P" IOSTANDARD = "LVCMOS25";
#NET "LA03_N" LOC = W8;
#NET "LA03_N" IOSTANDARD = "LVCMOS25";
#NET "LA03_P" LOC = V7;
##NET "LA03_P" IOSTANDARD = "LVCMOS25";
#NET "LA04_N" LOC = U8;
#NET "LA04_N" IOSTANDARD = "LVCMOS25";
#NET "LA04_P" LOC = T8;
#NET "LA04_P" IOSTANDARD = "LVCMOS25";
#NET "LA05_N" LOC = AB6;
#NET "LA05_N" IOSTANDARD = "LVCMOS25";
#NET "LA05_P" LOC = AA6;
#NET "LA05_P" IOSTANDARD = "LVCMOS25";
#NET "LA06_N" LOC = AB5;
#NET "LA06_N" IOSTANDARD = "LVCMOS25";
#NET "LA06_P" LOC = Y5;
#NET "LA06_P" IOSTANDARD = "LVCMOS25";
#NET "LA07_N" LOC = V9;
#NET "LA07_N" IOSTANDARD = "LVCMOS25";
#NET "LA07_P" LOC = U9;
#NET "LA07_P" IOSTANDARD = "LVCMOS25";
#NET "LA08_N" LOC = R8;
#NET "LA08_N" IOSTANDARD = "LVCMOS25";
#NET "LA08_P" LOC = R9;
#NET "LA08_P" IOSTANDARD = "LVCMOS25";
#NET "LA09_N" LOC = AB7;
#NET "LA09_N" IOSTANDARD = "LVCMOS25";
#NET "LA09_P" LOC = Y7;
#NET "LA09_P" IOSTANDARD = "LVCMOS25";
#NET "LA10_N" LOC = AB8;
#NET "LA10_N" IOSTANDARD = "LVCMOS25";
#NET "LA10_P" LOC = AA8;
#NET "LA10_P" IOSTANDARD = "LVCMOS25";
#NET "LA11_N" LOC = Y10;
#NET "LA11_N" IOSTANDARD = "LVCMOS25";
#NET "LA11_P" LOC = W10;
#NET "LA11_P" IOSTANDARD = "LVCMOS25";
#NET "LA12_N" LOC = U10;
#NET "LA12_N" IOSTANDARD = "LVCMOS25";
#NET "LA12_P" LOC = T10;
#NET "LA12_P" IOSTANDARD = "LVCMOS25";
#NET "LA13_N" LOC = AB9;
#NET "LA13_N" IOSTANDARD = "LVCMOS25";
#NET "LA13_P" LOC = Y9;
#NET "LA13_P" IOSTANDARD = "LVCMOS25";
#NET "LA14_N" LOC = AB4;
#NET "LA14_N" IOSTANDARD = "LVCMOS25";
#NET "LA14_P" LOC = AA4;
#NET "LA14_P" IOSTANDARD = "LVCMOS25";
#NET "LA15_N" LOC = W11;
#NET "LA15_N" IOSTANDARD = "LVCMOS25";
#NET "LA15_P" LOC = V11;
#NET "LA15_P" IOSTANDARD = "LVCMOS25";
#NET "LA16_N" LOC = AB15;
#NET "LA16_N" IOSTANDARD = "LVCMOS25";
#NET "LA16_P" LOC = Y15;
#NET "LA16_P" IOSTANDARD = "LVCMOS25";
#NET "LA17_N" LOC = AB13;
#NET "LA17_N" IOSTANDARD = "LVCMOS25";
#NET "LA17_P" LOC = Y13;
#NET "LA17_P" IOSTANDARD = "LVCMOS25";
#NET "LA18_N" LOC = U12;
#NET "LA18_N" IOSTANDARD = "LVCMOS25";
#NET "LA18_P" LOC = T12;
#NET "LA18_P" IOSTANDARD = "LVCMOS25";
#NET "LA19_N" LOC = Y12;
#NET "LA19_N" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = W12;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA20_N" LOC = T11;
#NET "LA20_N" IOSTANDARD = "LVCMOS25";
#NET "LA20_P" LOC = R11;
#NET "LA20_P" IOSTANDARD = "LVCMOS25";
#NET "LA21_N" LOC = W13;
#NET "LA21_N" IOSTANDARD = "LVCMOS25";
#NET "LA21_P" LOC = V13;
#NET "LA21_P" IOSTANDARD = "LVCMOS25";
#NET "LA22_N" LOC = T14;
#NET "LA22_N" IOSTANDARD = "LVCMOS25";
#NET "LA22_P" LOC = R13;
#NET "LA22_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "LA24_N" LOC = Y14;
#NET "LA24_N" IOSTANDARD = "LVCMOS25";
#NET "LA24_P" LOC = W14;
#NET "LA24_P" IOSTANDARD = "LVCMOS25";
#NET "LA25_N" LOC = U15;
#NET "LA25_N" IOSTANDARD = "LVCMOS25";
#NET "LA25_P" LOC = T15;
#NET "LA25_P" IOSTANDARD = "LVCMOS25";
#NET "LA26_N" LOC = AB17;
#NET "LA26_N" IOSTANDARD = "LVCMOS25";
#NET "LA26_P" LOC = Y17;
#NET "LA26_P" IOSTANDARD = "LVCMOS25";
#NET "LA27_N" LOC = AB18;
#NET "LA27_N" IOSTANDARD = "LVCMOS25";
#NET "LA27_P" LOC = AA18;
#NET "LA27_P" IOSTANDARD = "LVCMOS25";
#NET "LA28_N" LOC = W15;
#NET "LA28_N" IOSTANDARD = "LVCMOS25";
#NET "LA28_P" LOC = Y16;
#NET "LA28_P" IOSTANDARD = "LVCMOS25";
#NET "LA29_N" LOC = Y18;
#NET "LA29_N" IOSTANDARD = "LVCMOS25";
#NET "LA29_P" LOC = W17;
#NET "LA29_P" IOSTANDARD = "LVCMOS25";
#NET "LA30_N" LOC = W18;
#NET "LA30_N" IOSTANDARD = "LVCMOS25";
#NET "LA30_P" LOC = V17;
#NET "LA30_P" IOSTANDARD = "LVCMOS25";
#NET "LA31_N" LOC = C18;
#NET "LA31_N" IOSTANDARD = "LVCMOS25";
#NET "LA31_P" LOC = D17;
#NET "LA31_P" IOSTANDARD = "LVCMOS25";
#NET "LA32_N" LOC = A20;
#NET "LA32_N" IOSTANDARD = "LVCMOS25";
#NET "LA32_P" LOC = B20;
#NET "LA32_P" IOSTANDARD = "LVCMOS25";
#NET "LA33_N" LOC = A19;
#NET "LA33_N" IOSTANDARD = "LVCMOS25";
#NET "LA33_P" LOC = C19;
#NET "LA33_P" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SCL" LOC = AA14;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = AB14;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";#NET "DDR3_CAS_N" LOC = M4;
#NET "DDR3_CAS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CK_N" LOC = K3;
#NET "DDR3_CK_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CK_P" LOC = K4;
#NET "DDR3_CK_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_CKE" LOC = F2;
#NET "DDR3_CKE" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDM" LOC = N4;
#NET "DDR3_LDM" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDQS_N" LOC = N1;
#NET "DDR3_LDQS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_LDQS_P" LOC = N3;
#NET "DDR3_LDQS_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_ODT" LOC = L6;
#NET "DDR3_ODT" IOSTANDARD = "LVCMOS15";
#NET "DDR3_RAS_N" LOC = M5;
#NET "DDR3_RAS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_RESET_N" LOC = E3;
#NET "DDR3_RESET_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDM" LOC = P3;
#NET "DDR3_UDM" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDQS_N" LOC = V1;
#NET "DDR3_UDQS_N" IOSTANDARD = "LVCMOS15";
#NET "DDR3_UDQS_P" LOC = V2;
#NET "DDR3_UDQS_P" IOSTANDARD = "LVCMOS15";
#NET "DDR3_WE_N" LOC = H2;
#NET "DDR3_WE_N" IOSTANDARD = "LVCMOS15";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
#NET "PCB_VER[0]" LOC = P5;
#NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[1]" LOC = P4;
#NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[2]" LOC = AA2;
#NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[3]" LOC = AA1;
#NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[4]" LOC = N6;
#NET "PCB_VER[4]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[5]" LOC = N7;
#NET "PCB_VER[5]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[6]" LOC = U4;
#NET "PCB_VER[6]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[7]" LOC = T4;
#NET "PCB_VER[7]" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A0" LOC = K2;
#NET "DDR3_A0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A1" LOC = K1;
#NET "DDR3_A1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A2" LOC = K5;
#NET "DDR3_A2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A3" LOC = M6;
#NET "DDR3_A3" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A4" LOC = H3;
#NET "DDR3_A4" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A5" LOC = M3;
#NET "DDR3_A5" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A6" LOC = L4;
#NET "DDR3_A6" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A7" LOC = K6;
#NET "DDR3_A7" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A8" LOC = G3;
#NET "DDR3_A8" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A9" LOC = G1;
#NET "DDR3_A9" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A10" LOC = J4;
#NET "DDR3_A10" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A11" LOC = E1;
#NET "DDR3_A11" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A12" LOC = F1;
#NET "DDR3_A12" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A13" LOC = J6;
#NET "DDR3_A13" IOSTANDARD = "LVCMOS15";
#NET "DDR3_A14" LOC = H5;
#NET "DDR3_A14" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA0" LOC = J3;
#NET "DDR3_BA0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA1" LOC = J1;
#NET "DDR3_BA1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_BA2" LOC = H1;
#NET "DDR3_BA2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ0" LOC = R3;
#NET "DDR3_DQ0" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ1" LOC = R1;
#NET "DDR3_DQ1" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ2" LOC = P2;
#NET "DDR3_DQ2" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ3" LOC = P1;
#NET "DDR3_DQ3" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ4" LOC = L3;
#NET "DDR3_DQ4" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ5" LOC = L1;
#NET "DDR3_DQ5" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ6" LOC = M2;
#NET "DDR3_DQ6" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ7" LOC = M1;
#NET "DDR3_DQ7" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ8" LOC = T2;
#NET "DDR3_DQ8" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ9" LOC = T1;
#NET "DDR3_DQ9" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ10" LOC = U3;
#NET "DDR3_DQ10" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ11" LOC = U1;
#NET "DDR3_DQ11" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ12" LOC = W3;
#NET "DDR3_DQ12" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ13" LOC = W1;
#NET "DDR3_DQ13" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ14" LOC = Y2;
#NET "DDR3_DQ14" IOSTANDARD = "LVCMOS15";
#NET "DDR3_DQ15" LOC = Y1;
#NET "DDR3_DQ15" IOSTANDARD = "LVCMOS15";
NET "L_CLKp" TNM_NET = "l_clkp_grp";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
########################################################
## Pin definitions for FmcDio5chttl + SPEC v1.1/2.0 ##
########################################################
# DIO outputs
NET "dio_p_o[4]" LOC= T8;
NET "dio_n_o[4]" LOC= U8;
NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
NET "dio_n_o[4]" IOSTANDARD=LVDS_25;
NET "dio_p_o[3]" LOC= U9;
NET "dio_n_o[3]" LOC= V9;
NET "dio_p_o[3]" IOSTANDARD=LVDS_25;
NET "dio_n_o[3]" IOSTANDARD=LVDS_25;
NET "dio_p_o[2]" LOC= R9;
NET "dio_n_o[2]" LOC= R8;
NET "dio_p_o[2]" IOSTANDARD=LVDS_25;
NET "dio_n_o[2]" IOSTANDARD=LVDS_25;
NET "dio_p_o[1]" LOC= Y16;
NET "dio_n_o[1]" LOC= W15;
NET "dio_p_o[1]" IOSTANDARD=LVDS_25;
NET "dio_n_o[1]" IOSTANDARD=LVDS_25;
NET "dio_p_o[0]" LOC= W17;
NET "dio_n_o[0]" LOC= Y18;
NET "dio_p_o[0]" IOSTANDARD=LVDS_25;
NET "dio_n_o[0]" IOSTANDARD=LVDS_25;
NET "dio_sdn_n_o" LOC= V11;
NET "dio_sdn_n_o" IOSTANDARD=LVCMOS25;
NET "dio_sdn_ck_n_o" LOC= Y5;
NET "dio_sdn_ck_n_o" IOSTANDARD=LVCMOS25;
# DIO output enable/termination enable
NET "dio_oe_n_o[4]" LOC= AA6;
NET "dio_oe_n_o[3]" LOC= W10;
NET "dio_oe_n_o[2]" LOC= W11;
NET "dio_oe_n_o[1]" LOC= Y14;
NET "dio_oe_n_o[0]" LOC= V17;
NET "dio_oe_n_o[4]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[3]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[2]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[1]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[0]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[4]" LOC=AB7;
NET "dio_term_en_o[3]" LOC=Y7;
NET "dio_term_en_o[2]" LOC=AB6;
NET "dio_term_en_o[1]" LOC=AB5;
NET "dio_term_en_o[0]" LOC=W18;
NET "dio_term_en_o[4]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[3]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[2]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[1]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[0]" IOSTANDARD=LVCMOS25;
NET "dio_onewire_b" LOC=AB16;
NET "dio_onewire_b" IOSTANDARD=LVCMOS25;
# DIO inputs
NET "dio_clk_p_i" LOC=L20;
NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
NET "dio_clk_n_i" LOC=L22;
NET "dio_clk_n_i" IOSTANDARD=LVDS_25;
NET "dio_p_i[4]" LOC =Y11;
NET "dio_p_i[4]" IOSTANDARD=LVDS_25;
NET "dio_n_i[4]" LOC =AB11;
NET "dio_n_i[4]" IOSTANDARD=LVDS_25;
NET "dio_p_i[3]" LOC =V7;
NET "dio_p_i[3]" IOSTANDARD=LVDS_25;
NET "dio_n_i[3]" LOC =W8;
NET "dio_n_i[3]" IOSTANDARD=LVDS_25;
NET "dio_p_i[2]" LOC =W12;
NET "dio_p_i[2]" IOSTANDARD=LVDS_25;
NET "dio_n_i[2]" LOC =Y12;
NET "dio_n_i[2]" IOSTANDARD=LVDS_25;
NET "dio_p_i[1]" LOC =R11;
NET "dio_p_i[1]" IOSTANDARD=LVDS_25;
NET "dio_n_i[1]" LOC =T11;
NET "dio_n_i[1]" IOSTANDARD=LVDS_25;
NET "dio_p_i[0]" LOC =C19;
NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
NET "dio_n_i[0]" LOC =A19;
NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
NET "dio_led_top_o" LOC= AA12;
NET "dio_led_top_o" IOSTANDARD=LVCMOS25;
NET "dio_led_bot_o" LOC= AB12;
NET "dio_led_bot_o" IOSTANDARD=LVCMOS25;
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
# System clock
# DDR3
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_GTP/U_Rbclk_bufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
NET "U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
\ No newline at end of file
top/spec_1_1/wr_core_demo/spec_top.vhd 0 → 100644
View file @ b2edc7ba
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wbconmax_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
generic
(
TAR_ADDR_WDTH : integer := 13 -- not used for this project
);
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
LED_RED : out std_logic;
LED_GREEN : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_cs1_n_o : out std_logic;
dac_cs2_n_o : out std_logic;
fpga_scl_b : inout std_logic;
fpga_sda_b : inout std_logic;
button1_i : inout std_logic;
button2_i : inout std_logic;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_b : inout std_logic; -- rate_select
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
-------------------------------------------------------------------------
-- Digital I/O FMC Pins
-------------------------------------------------------------------------
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
-----------------------------------------
--UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end spec_top;
architecture rtl of spec_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component gn4124_core
generic(
-- g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26; -- DMA wishbone address bus width;
g_CSR_WB_MODE : string := "classic"
);
port
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-priv_log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
);
end component; -- gn4124_core
component wr_core
generic (
g_simulation : integer;
g_virtual_uart : natural;
g_ep_rxbuf_size_log2 : integer;
g_dpram_initf : string;
g_dpram_size : integer;
g_num_gpio : integer);
port (
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
pps_p_o : out std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
gpio_o : out std_logic_vector(g_num_gpio-1 downto 0);
gpio_i : in std_logic_vector(g_num_gpio-1 downto 0);
gpio_dir_o : out std_logic_vector(g_num_gpio-1 downto 0);
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wb_addr_i : in std_logic_vector(c_aw-1 downto 0);
wb_data_i : in std_logic_vector(c_dw-1 downto 0);
wb_data_o : out std_logic_vector(c_dw-1 downto 0);
wb_sel_i : in std_logic_vector(c_sw-1 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
genrest_n : out std_logic;
dio_o : out std_logic_vector(3 downto 0));
end component;
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_ch0_use_refclk_out : boolean := false;
g_ch1_use_refclk_out : boolean := false);
port (
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_ref_clk_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
component spec_serial_dac_arb
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_clr_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
signal rst : std_logic;
-- CSR wishbone bus
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal spi_wb_adr : std_logic_vector(4 downto 0);
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(29 downto 0);
signal irq_to_gn4124 : std_logic;
-- SPI
signal spi_slave_select : std_logic_vector(7 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_rst_n : std_logic;
signal led_divider : unsigned(23 downto 0);
signal wrc_gpio_out : std_logic_vector(7 downto 0);
signal wrc_gpio_in : std_logic_vector(7 downto 0);
signal wrc_gpio_dir : std_logic_vector(7 downto 0);
signal wb_adr_wrc : std_logic_vector(17 downto 0);
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal local_reset_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
begin
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_dmtd,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf);
--p_gen_reset : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- button1_synced(0) <= button1_i;
-- button1_synced(1) <= button1_synced(0);
-- button1_synced(2) <= button1_synced(1);
-- if(L_RST_N = '0') then
-- local_reset_n <= '0';
-- elsif (button1_synced(2) = '0') then
-- local_reset_n <= '0';
-- else
-- local_reset_n <= '1';
-- end if;
-- end if;
--end process;
local_reset_n <= L_RST_N;
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
rst <= not(L_RST_N);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
-- g_IS_SPARTAN6 => true,
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH,
g_CSR_WB_MODE => "classic"
)
port map
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i => L_RST_N,
-- P2L clock PLL locked
p2l_pll_locked => p2l_pll_locked,
-- Debug outputs
debug_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => GPIO(0),
---------------------------------------------------------
-- Target Interface (Wishbone master)
wb_clk_i => clk_sys,
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
dma_clk_i => clk_sys,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall
);
process(clk_sys, rst)
begin
if rising_edge(clk_sys) then
led_divider <= led_divider + 1;
end if;
end process;
-- LED_RED <= std_logic(led_divider(led_divider'high));
wb_adr_wrc <= '0' & wb_adr (16 downto 0);
U_WR_CORE : wr_core
generic map (
g_simulation => 0,
g_virtual_uart => 0,
g_ep_rxbuf_size_log2 => 12,
g_dpram_initf => "",
g_dpram_size => 16384,
g_num_gpio => 8)
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
rst_n_i => local_reset_n,
pps_p_o => pps,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
gpio_o => wrc_gpio_out,
gpio_i => wrc_gpio_in,
gpio_dir_o => wrc_gpio_dir,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wb_addr_i => wb_adr_wrc,
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(31 downto 0),
wb_sel_i => wb_sel,
wb_we_i => wb_we,
wb_cyc_i => wb_cyc(0),
wb_stb_i => wb_stb,
wb_ack_o => wb_ack(0),
genrest_n => open,
dio_o => dio_out(4 downto 1),
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen
);
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => 0)
port map (
ch0_ref_clk_i => clk_125m_pllref,
ch0_ref_clk_o => open,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_ref_clk_o => open,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => dac_cs1_n_o,
dac_cs_n_o(1) => dac_cs2_n_o,
dac_clr_n_o => dac_clr_n_o,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
U_Extend_PPS : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_125m_pllref,
rst_n_i => local_reset_n,
pulse_i => pps,
extended_o => dio_led_top_o);
gen_dio_iobufs : for i in 0 to 4 generate
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i)
);
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
U_input_buffer : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_clk,
I => dio_clk_p_i,
IB => dio_clk_n_i
);
dio_led_bot_o <= '0';
dio_out(0) <= pps;
-- dio_out(4 downto 1) <= (others => '0');
dio_oe_n_o(0) <= '0';
dio_oe_n_o(4 downto 1) <= (others => '0');
dio_term_en_o <= (others => '0');
dio_sdn_ck_n_o <= '0';
dio_sdn_n_o <= '0';
LED_GREEN <= wrc_gpio_out(0);
LED_RED <= wrc_gpio_out(1);
fpga_scl_b <= '0' when wrc_gpio_out(2) = '0' else 'Z';
fpga_sda_b <= '0' when wrc_gpio_out(3) = '0' else 'Z';
wrc_gpio_in(4) <= fpga_sda_b;
wrc_gpio_in(5) <= '0';
wrc_gpio_in(6) <= button2_i;
sfp_mod_def0_b <= '0';
sfp_mod_def1_b <= '0';
sfp_mod_def2_b <= '0';
sfp_tx_disable_o <= '0';
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_125m_pllref,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL
-- );
--TRIG0(7 downto 0)<=phy_tx_data;
--TRIG0(8) <= phy_tx_k;
--TRIG0(9) <= phy_tx_disparity;
--TRIG0(10) <= phy_tx_enc_err;
end rtl;
top/spec_1_1/wr_core_demo/wb_gpio_port_notristates.vhd 0 → 100644
View file @ b2edc7ba
------------------------------------------------------------------------------
-- Title : Wishbone GPIO port
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-04-06
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Bidirectional GPIO port of configurable width (1 to 32 bits).
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_gpio_port_notristates is
generic(g_num_pins : natural := 8 -- number of GPIO pins
);
port(
-- System reset, active low
sys_rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
-- GPIO pin vector
gpio_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_dir_o : out std_logic_vector(g_num_pins-1 downto 0)
);
end wb_gpio_port_notristates;
architecture behavioral of wb_gpio_port_notristates is
constant c_GPIO_REG_CODR : std_logic_vector(2 downto 0) := "000"; -- *reg* clear output register
constant c_GPIO_REG_SODR : std_logic_vector(2 downto 0) := "001"; -- *reg* set output register
constant c_GPIO_REG_DDR : std_logic_vector(2 downto 0) := "010"; -- *reg* data direction register
constant c_GPIO_REG_PSR : std_logic_vector(2 downto 0) := "011"; -- *reg* pin state register
signal out_reg, in_reg, dir_reg : std_logic_vector(g_num_pins-1 downto 0);
signal gpio_in_synced : std_logic_vector(g_num_pins-1 downto 0);
signal ack_int : std_logic;
begin
GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
INPUT_SYNC : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => sys_rst_n_i,
clk_i => wb_clk_i,
data_i => gpio_i(i),
synced_o => gpio_in_synced(i),
npulse_o => open
);
end generate GEN_SYNC_FFS;
process (wb_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dir_reg <= (others => '0');
out_reg <= (others => '0');
ack_int <= '0';
wb_data_o(g_num_pins-1 downto 0) <= (others => '0');
elsif rising_edge(wb_clk_i) then
if(ack_int = '1') then
ack_int <= '0';
elsif(wb_cyc_i = '1') and (wb_sel_i = '1') and (wb_stb_i = '1') then
if(wb_we_i = '1') then
case wb_addr_i(2 downto 0) is
when c_GPIO_REG_SODR =>
out_reg <= out_reg or wb_data_i(g_num_pins-1 downto 0);
ack_int <= '1';
when c_GPIO_REG_CODR =>
out_reg <= out_reg and (not wb_data_i(g_num_pins-1 downto 0));
ack_int <= '1';
when c_GPIO_REG_DDR =>
dir_reg <= wb_data_i(g_num_pins-1 downto 0);
ack_int <= '1';
when others =>
ack_int <= '1';
end case;
else
case wb_addr_i(2 downto 0) is
when c_GPIO_REG_DDR =>
wb_data_o(g_num_pins-1 downto 0) <= dir_reg;
ack_int <= '1';
when c_GPIO_REG_PSR =>
wb_data_o(g_num_pins-1 downto 0) <= gpio_in_synced;
ack_int <= '1';
when others =>
ack_int <= '1';
end case;
end if;
else
ack_int <= '0';
end if;
end if;
end process;
gpio_dir_o <= dir_reg;
gpio_o <= out_reg;
wb_ack_o <= ack_int;
end behavioral;
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