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White Rabbit core collection
Commits
0f14c50b
Commit
0f14c50b
authored
Oct 25, 2011
by
Tomasz Wlostowski
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WR core: imported from master branch
parent
9d212620
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wb_reset.vhd
modules/wrc_core/wb_reset.vhd
+96
-0
wr_core.vhd
modules/wrc_core/wr_core.vhd
+723
-0
wrc_dpram.vhd
modules/wrc_core/wrc_dpram.vhd
+116
-0
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+294
-0
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+317
-0
No files found.
modules/wrc_core/wb_reset.vhd
0 → 100644
View file @
0f14c50b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core ZPU reset generator
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_reset.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-06-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WB_RESET is a reset signal generator for ZPU. It is controlled by wishbone
-- and is used by ZPU firmware loader(zpu-loader) to reset the processor during
-- copying the binary to dpram.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_reset
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
genrst_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
wb_reset
;
architecture
behaviour
of
wb_reset
is
constant
c_RST_REG
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
signal
rst_reg
:
std_logic_vector
(
7
downto
0
);
signal
grst_n
:
std_logic_vector
(
20
downto
0
);
signal
ack_int
:
std_logic
;
begin
process
(
clk_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_int
<=
'0'
;
rst_reg
<=
(
others
=>
'0'
);
elsif
(
rising_edge
(
clk_i
))
then
if
(
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
and
ack_int
=
'0'
)
then
if
(
wb_we_i
=
'1'
)
then
case
wb_addr_i
is
when
c_RST_REG
=>
rst_reg
<=
wb_data_i
(
7
downto
0
);
when
others
=>
end
case
;
end
if
;
ack_int
<=
'1'
;
else
ack_int
<=
'0'
;
end
if
;
end
if
;
end
process
;
wb_ack_o
<=
ack_int
;
process
(
clk_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
grst_n
<=
(
others
=>
'1'
);
elsif
(
rising_edge
(
clk_i
))
then
if
(
rst_reg
(
0
)
=
'1'
)
then
grst_n
(
0
)
<=
'0'
;
else
grst_n
(
0
)
<=
'1'
;
end
if
;
grst_n
(
grst_n
'left
downto
1
)
<=
grst_n
(
grst_n
'left
-1
downto
0
);
end
if
;
end
process
;
genrst_n_o
<=
grst_n
(
grst_n
'left
);
end
behaviour
;
modules/wrc_core/wr_core.vhd
0 → 100644
View file @
0f14c50b
This diff is collapsed.
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modules/wrc_core/wrc_dpram.vhd
0 → 100644
View file @
0f14c50b
-------------------------------------------------------------------------------
-- Title : Dual-port RAM for WR core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_dpram.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-15
-- Last update: 2011-07-18
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Dual port RAM from genrams with wishbone interface
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-15 1.0 greg.d Created
-- 2011-06-09 1.01 twlostow Removed unnecessary generics
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
genram_pkg
.
all
;
entity
wrc_dpram
is
generic
(
g_size
:
natural
:
=
16384
;
-- 16 * 32bit = 64kB
g_init_file
:
string
:
=
""
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
--PORT A (Wishbone)
wb_addr_i
:
in
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
--PORT B (miniNIC)
mem_addr_i
:
in
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
mem_data_i
:
in
std_logic_vector
(
31
downto
0
);
mem_data_o
:
out
std_logic_vector
(
31
downto
0
);
mem_wr_i
:
in
std_logic
);
end
wrc_dpram
;
architecture
struct
of
wrc_dpram
is
signal
s_wb_ack_o
:
std_logic
;
signal
muxed_we
:
std_logic
;
signal
s_bwea
:
std_logic_vector
(
3
downto
0
);
signal
s_bweb
:
std_logic_vector
(
3
downto
0
);
begin
wb_ack_o
<=
s_wb_ack_o
;
DPRAM
:
generic_dpram
generic
map
(
-- standard parameters
g_data_width
=>
32
,
g_size
=>
g_size
,
g_with_byte_enable
=>
true
,
g_addr_conflict_resolution
=>
"read_first"
,
g_init_file
=>
g_init_file
,
g_dual_clock
=>
false
)
port
map
(
rst_n_i
=>
rst_n_i
,
-- Port A
clka_i
=>
clk_i
,
bwea_i
=>
s_bwea
,
wea_i
=>
muxed_we
,
--wb_we_i,
aa_i
=>
wb_addr_i
,
da_i
=>
wb_data_i
,
qa_o
=>
wb_data_o
,
-- Port B
clkb_i
=>
clk_i
,
bweb_i
=>
s_bweb
,
web_i
=>
mem_wr_i
,
ab_i
=>
mem_addr_i
,
db_i
=>
mem_data_i
,
qb_o
=>
mem_data_o
);
s_bwea
<=
wb_sel_i
when
(
wb_we_i
=
'1'
and
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
)
else
"0000"
;
s_bweb
<=
(
others
=>
mem_wr_i
);
muxed_we
<=
wb_we_i
when
(
wb_stb_i
=
'1'
and
wb_cyc_i
=
'1'
)
else
'0'
;
process
(
clk_i
)
begin
if
(
rising_edge
(
clk_i
))
then
if
(
rst_n_i
=
'0'
)
then
s_wb_ack_o
<=
'0'
;
else
if
(
s_wb_ack_o
=
'1'
)
then
s_wb_ack_o
<=
'0'
;
else
s_wb_ack_o
<=
wb_cyc_i
and
wb_stb_i
;
end
if
;
end
if
;
end
if
;
end
process
;
end
struct
;
modules/wrc_core/wrc_periph.vhd
0 → 100644
View file @
0f14c50b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core peripherials
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_periph.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-07-18
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WRC_PERIPH is a single WB slave which includes all 'small' WB peripherials
-- needed for WR PTP Core. It has: wb_gpio_port, wb_simple_uart, wb_tics and
-- wb_reset.
-- All those modules share Wishbone Slave interface, and the address bus is
-- used to choose one of them at a time.
--
-- wb_addr_i(11:0):
-- (11) -> select wb_reset
-- (10) -> select wb_tics
-- (9) -> select wb_uart
-- (8) -> select wb_gpio
-- (7:0)-> address shared between wb modules inside wrc_periph
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
wrcore_pkg
.
all
;
entity
wrc_periph
is
generic
(
g_gpio_pins
:
natural
:
=
8
;
g_virtual_uart
:
natural
:
=
0
;
g_tics_period
:
integer
);
port
(
clk_sys_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
gpio_o
:
out
std_logic_vector
(
g_gpio_pins
-1
downto
0
);
gpio_i
:
in
std_logic_vector
(
g_gpio_pins
-1
downto
0
);
gpio_dir_o
:
out
std_logic_vector
(
g_gpio_pins
-1
downto
0
);
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
genrst_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
11
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
wrc_periph
;
architecture
struct
of
wrc_periph
is
component
wb_tics
generic
(
g_period
:
integer
);
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
;
component
wb_reset
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
genrst_n_o
:
out
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
;
component
wb_simple_uart
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
);
end
component
;
component
wb_virtual_uart
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
);
end
component
;
component
wb_gpio_port
generic
(
g_num_pins
:
natural
;
g_with_builtin_tristates
:
boolean
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_ack_o
:
out
std_logic
;
gpio_out_o
:
out
std_logic_vector
(
g_num_pins
-1
downto
0
);
gpio_in_i
:
in
std_logic_vector
(
g_num_pins
-1
downto
0
);
gpio_oen_o
:
out
std_logic_vector
(
g_num_pins
-1
downto
0
));
end
component
;
type
t_wbdata
is
array
(
3
downto
0
)
of
std_logic_vector
(
31
downto
0
);
signal
wb_cycs_i
:
std_logic_vector
(
3
downto
0
);
signal
wb_stbs_i
:
std_logic_vector
(
3
downto
0
);
signal
wb_acks_o
:
std_logic_vector
(
3
downto
0
);
signal
wb_dats_o
:
t_wbdata
;
signal
wb_ack_int
:
std_logic
;
begin
--TRIG3(11 downto 0) <= wb_addr_i(11 downto 0);
-- TRIG3(21 downto 12) <= (others => '0');
-- TRIG3(31 downto 28) <= wb_sel_i;
-- TRIG3(22) <= wb_cyc_i;
-- TRIG3(23) <= wb_stb_i;
-- TRIG3(24) <= wb_we_i;
-- TRIG3(25) <= wb_ack_int;
-- TRIG0 <= wb_data_i;
-- TRIG2(3 downto 0) <= wb_cycs_i;
-- TRIG2(7 downto 4) <= wb_acks_o;
wb_ack_o
<=
wb_ack_int
;
GENWB
:
for
I
in
0
to
3
generate
wb_cycs_i
(
I
)
<=
wb_cyc_i
and
wb_addr_i
(
8
+
I
);
wb_stbs_i
(
I
)
<=
wb_stb_i
and
wb_addr_i
(
8
+
I
);
end
generate
;
wb_ack_int
<=
wb_acks_o
(
0
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0001"
)
else
wb_acks_o
(
1
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0010"
)
else
wb_acks_o
(
2
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0100"
)
else
wb_acks_o
(
3
)
when
(
wb_addr_i
(
11
downto
8
)
=
"1000"
)
else
'0'
;
wb_data_o
<=
wb_dats_o
(
0
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0001"
)
else
wb_dats_o
(
1
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0010"
)
else
wb_dats_o
(
2
)
when
(
wb_addr_i
(
11
downto
8
)
=
"0100"
)
else
wb_dats_o
(
3
)
when
(
wb_addr_i
(
11
downto
8
)
=
"1000"
)
else
(
others
=>
'0'
);
GPIO
:
wb_gpio_port
generic
map
(
g_num_pins
=>
g_gpio_pins
,
g_with_builtin_tristates
=>
false
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_sel_i
=>
wb_sel_i
(
0
),
wb_cyc_i
=>
wb_cycs_i
(
0
),
wb_stb_i
=>
wb_stb_i
,
wb_we_i
=>
wb_we_i
,
wb_adr_i
=>
wb_addr_i
(
5
downto
0
),
wb_dat_i
=>
wb_data_i
,
wb_dat_o
=>
wb_dats_o
(
0
),
wb_ack_o
=>
wb_acks_o
(
0
),
gpio_out_o
=>
gpio_o
,
gpio_in_i
=>
gpio_i
,
gpio_oen_o
=>
gpio_dir_o
);
GEN_UART
:
if
(
g_virtual_uart
=
0
)
generate
UART
:
wb_simple_uart
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wb_addr_i
=>
wb_addr_i
(
1
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
1
),
wb_cyc_i
=>
wb_cycs_i
(
1
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stb_i
,
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
1
),
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
);
end
generate
;
GEN_VIRTUART
:
if
(
g_virtual_uart
=
1
)
generate
VIRTUAL_UART
:
wb_virtual_uart
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_addr_i
=>
wb_addr_i
(
2
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
1
),
wb_cyc_i
=>
wb_cycs_i
(
1
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stb_i
,
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
1
)
);
end
generate
;
TICS
:
wb_tics
generic
map
(
g_period
=>
g_tics_period
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wb_addr_i
=>
wb_addr_i
(
1
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
2
),
wb_cyc_i
=>
wb_cycs_i
(
2
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stb_i
,
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
2
)
);
RST_GEN
:
wb_reset
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
genrst_n_o
=>
genrst_n_o
,
wb_addr_i
=>
wb_addr_i
(
1
downto
0
),
wb_data_i
=>
wb_data_i
,
wb_data_o
=>
wb_dats_o
(
3
),
wb_sel_i
=>
wb_sel_i
,
wb_stb_i
=>
wb_stbs_i
(
3
),
wb_cyc_i
=>
wb_cycs_i
(
3
),
wb_we_i
=>
wb_we_i
,
wb_ack_o
=>
wb_acks_o
(
3
)
);
end
struct
;
modules/wrc_core/wrcore_pkg.vhd
0 → 100644
View file @
0f14c50b
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