Commit b2edc7ba authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wr_minic: added structized wrapper + updated Manifest

parent 0f14c50b
files = [ "minic_packet_buffer.vhd",
"minic_wb_slave.vhd",
"minic_wbgen2_pkg.vhd",
"wr_mini_nic.vhd" ];
"minic_wb_slave.vhd",
"minic_wbgen2_pkg.vhd",
"wr_mini_nic.vhd",
"xwr_mini_nic.vhd" ];
library ieee;
use ieee.std_logic_1164.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
entity xwr_mini_nic is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_memsize_log2 : integer := 14;
g_buffer_little_endian : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- System memory i/f
-------------------------------------------------------------------------------
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
-------------------------------------------------------------------------------
-- Pipelined Wishbone interface
-------------------------------------------------------------------------------
-- WBP Master (TX)
src_o: out t_wrf_source_out;
src_i: in t_wrf_source_in;
-- WBP Slave (RX)
snk_o: out t_wrf_sink_out;
snk_i: in t_wrf_sink_in;
-------------------------------------------------------------------------------
-- TXTSU i/f
-------------------------------------------------------------------------------
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone slave
-------------------------------------------------------------------------------
wb_i: in t_wishbone_slave_in;
wb_o: out t_wishbone_slave_out
);
end xwr_mini_nic;
architecture wrapper of xwr_mini_nic is
component wr_mini_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_err_i : in std_logic;
src_ack_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_err_o : out std_logic;
snk_ack_o : out std_logic;
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic);
end component;
begin -- wrapper
wr_mini_nic_1: wr_mini_nic
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_memsize_log2 => g_memsize_log2,
g_buffer_little_endian => g_buffer_little_endian)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
mem_data_o => mem_data_o,
mem_addr_o => mem_addr_o,
mem_data_i => mem_data_i,
mem_wr_o => mem_wr_o,
src_dat_o => src_o.dat,
src_adr_o => src_o.adr,
src_sel_o => src_o.sel,
src_cyc_o => src_o.cyc,
src_stb_o => src_o.stb,
src_we_o => src_o.we,
src_stall_i => src_i.stall,
src_err_i => src_i.err,
src_ack_i => src_i.ack,
snk_dat_i => snk_i.dat,
snk_adr_i => snk_i.adr,
snk_sel_i => snk_i.sel,
snk_cyc_i => snk_i.cyc,
snk_stb_i => snk_i.stb,
snk_we_i => snk_i.we,
snk_stall_o => snk_o.stall,
snk_err_o => snk_o.err,
snk_ack_o => snk_o.ack,
txtsu_port_id_i => txtsu_port_id_i,
txtsu_frame_id_i => txtsu_frame_id_i,
txtsu_tsval_i => txtsu_tsval_i,
txtsu_valid_i => txtsu_valid_i,
txtsu_ack_o => txtsu_ack_o,
wb_cyc_i => wb_i.cyc,
wb_stb_i => wb_i.stb,
wb_we_i => wb_i.we,
wb_sel_i => wb_i.sel,
wb_adr_i => wb_i.adr,
wb_dat_i => wb_i.dat,
wb_dat_o => wb_o.dat,
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
wb_irq_o => wb_o.int);
end wrapper;
files = [ "wr_core.vhd",
"wrc_dpram.vhd",
"wrcore_pkg.vhd",
"wrc_periph.vhd",
"wb_reset.vhd" ];
fetchto = "../../ip_cores"
......@@ -10,5 +10,8 @@ files = [ "wrc_lm32.vhd",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_interrupt.v",
"lm32_dp_ram.v"
"lm32_dp_ram.v",
"lm32_debug.v",
"lm32_jtag.v",
"jtag_wb.v"
];
\ No newline at end of file
/* Added by GSI to support debug over wishbone */
`define ACK_DELAY 8 /* Give the JTAG core time to latch after a write */
module jtag_wb (
clk_i,
DAT_I,
ADR_I,
CYC_I,
SEL_I,
STB_I,
WE_I,
reg_d,
reg_addr_d,
ACK_O,
STALL_O,
DAT_O,
reg_update,
reg_q,
reg_addr_q,
jtck,
jrstn
);
input clk_i;
input [`LM32_WORD_RNG] DAT_I;
input [`LM32_WORD_RNG] ADR_I;
input CYC_I;
input [`LM32_BYTE_SELECT_RNG] SEL_I;
input STB_I;
input WE_I;
input [7:0] reg_d;
input [2:0] reg_addr_d;
output ACK_O;
output STALL_O;
output [`LM32_WORD_RNG] DAT_O;
output reg_update;
output [7:0] reg_q;
output [2:0] reg_addr_q;
output jtck;
output jrstn;
reg [7:0] reg_q;
reg [2:0] reg_addr_q;
reg [`ACK_DELAY-1:0] ack_shift;
assign reg_update = (CYC_I == `TRUE) &&
(STB_I == `TRUE) &&
(WE_I == `TRUE);
assign DAT_O[31:11] = 21'h0;
assign DAT_O[10:3] = reg_d;
assign DAT_O[2:0] = reg_addr_d;
assign jtck = clk_i;
assign jrstn = 1;
assign ACK_O = ack_shift[0];
assign STALL_O = |ack_shift[`ACK_DELAY-1:1];
always @(posedge clk_i)
begin
ack_shift <=
{CYC_I == `TRUE && STB_I == `TRUE && STALL_O == `FALSE,
ack_shift[`ACK_DELAY-1:1]};
if (reg_update == `TRUE)
begin
reg_q <= DAT_I[10:3];
reg_addr_q <= DAT_I[2:0];
end
end
endmodule
......@@ -182,7 +182,7 @@ begin
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
endcase
end
end
endgenerate
......@@ -191,72 +191,91 @@ endgenerate
// Sequential Logic
/////////////////////////////////////////////////////
`define IE_DELAY 10
reg [`IE_DELAY:0] eie_delay = 0;
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
if(eie_delay[0])
ie <= eie;
eie_delay <= {1'b0, eie_delay[`IE_DELAY:1]};
if (eret_q_x == `TRUE) begin
// Restore interrupt enable
ie <= eie;
eie_delay[`IE_DELAY] <= `TRUE;
eie_delay[`IE_DELAY-1:0] <= 0;
end
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
im <= csr_write_data[interrupts-1:0];
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
......@@ -266,64 +285,74 @@ else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
bie <= `FALSE;
`endif
ip <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= asserted;
ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
begin
if(eie_delay[0])
ie <= eie;
eie_delay <= {1'b0, eie_delay[`IE_DELAY:1]};
if (eret_q_x == `TRUE) begin
// Restore interrupt enable
ie <= eie;
eie_delay[`IE_DELAY] <= `TRUE;
eie_delay[`IE_DELAY-1:0] <= 0;
end
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= csr_write_data[0];
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
end
......
......@@ -51,6 +51,14 @@ module lm32_top (
I_ACK_I,
I_ERR_I,
I_RTY_I,
`endif
`ifdef CFG_JWB_ENABLED
J_DAT_I,
J_ADR_I,
J_CYC_I,
J_SEL_I,
J_STB_I,
J_WE_I,
`endif
// Data Wishbone master
D_DAT_I,
......@@ -75,6 +83,10 @@ module lm32_top (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
`endif
`ifdef CFG_JWB_ENABLED
J_ACK_O,
J_DAT_O,
`endif
// Data Wishbone master
D_DAT_O,
......@@ -85,7 +97,10 @@ module lm32_top (
D_WE_O,
D_CTI_O,
D_LOCK_O,
D_BTE_O
D_BTE_O,
trace_pc_o,
trace_eret_o,
trace_pc_valid_o
);
/////////////////////////////////////////////////////
......@@ -111,6 +126,15 @@ input I_ERR_I; // Instruction Wishbone interfac
input I_RTY_I; // Instruction Wishbone interface retry
`endif
`ifdef CFG_JWB_ENABLED
input [`LM32_WORD_RNG] J_DAT_I;
input [`LM32_WORD_RNG] J_ADR_I;
input J_CYC_I;
input [`LM32_BYTE_SELECT_RNG] J_SEL_I;
input J_STB_I;
input J_WE_I;
`endif
input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
input D_ACK_I; // Data Wishbone interface acknowledgement
input D_ERR_I; // Data Wishbone interface error
......@@ -152,6 +176,13 @@ output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interfac
wire [`LM32_BTYPE_RNG] I_BTE_O;
`endif
`ifdef CFG_JWB_ENABLED
output J_ACK_O;
wire J_ACK_O;
output [`LM32_WORD_RNG] J_DAT_O;
wire [`LM32_WORD_RNG] J_DAT_O;
`endif
output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
wire [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
......@@ -199,6 +230,21 @@ wire trace_bret; // Indicates a bret instruction
`endif
`endif
output [31:0] trace_pc_o;
output trace_pc_valid_o;
output trace_eret_o;
`ifdef CFG_TRACE_ENABLED
assign trace_eret_o = trace_eret;
assign trace_pc_o =trace_pc;
assign trace_pc_valid_o = trace_pc_valid;
`else
assign trace_eret_o = 0;
assign trace_pc_o = 0;
assign trace_pc_valid_o = 0;
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
......@@ -276,7 +322,7 @@ lm32_cpu cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
`endif
`endif
// Data Wishbone master
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
......@@ -290,6 +336,29 @@ lm32_cpu cpu (
);
`ifdef CFG_JTAG_ENABLED
`ifdef CFG_JWB_ENABLED
jtag_wb jtag_wb (
// ----- Inputs -----
.clk_i (clk_i),
.DAT_I (J_DAT_I),
.ADR_I (J_ADR_I),
.CYC_I (J_CYC_I),
.SEL_I (J_SEL_I),
.STB_I (J_STB_I),
.WE_I (J_WE_I),
.reg_d (jtag_reg_d),
.reg_addr_d (jtag_reg_addr_d),
// ----- Outputs -----
.ACK_O (J_ACK_O),
.STALL_O (open),
.DAT_O (J_DAT_O),
.reg_update (jtag_update),
.reg_q (jtag_reg_q),
.reg_addr_q (jtag_reg_addr_q),
.jtck (jtck),
.jrstn (jrstn)
);
`else
// JTAG cores
jtag_cores jtag_cores (
// ----- Inputs -----
......@@ -302,6 +371,7 @@ jtag_cores jtag_cores (
.jtck (jtck),
.jrstn (jrstn)
);
`endif
`endif
`endif
endmodule
......@@ -36,12 +36,15 @@
//`define CFG_DCACHE_LIMIT 32'h7fffffff
// Enable Debugging
//`define CFG_JTAG_ENABLED
//`define CFG_JTAG_UART_ENABLED
//`define CFG_DEBUG_ENABLED
//`define CFG_HW_DEBUG_ENABLED
//`define CFG_BREAKPOINTS 32'h0
//`define CFG_WATCHPOINTS 32'h0
`define CFG_TRACE_ENABLED
`define CFG_JTAG_ENABLED
`define CFG_JTAG_UART_ENABLED
`define CFG_DEBUG_ENABLED
`define CFG_HW_DEBUG_ENABLED
`define CFG_BREAKPOINTS 32'h4
`define CFG_WATCHPOINTS 32'h4
`define CFG_JWB_ENABLED
`define CFG_INTERRUPTS_ENABLED
//`define CFG_BUS_ERRORS_ENABLED
......
......@@ -18,6 +18,8 @@ entity wrc_lm32 is
iwb_dat_i : in std_logic_vector(31 downto 0);
iwb_cyc_o : out std_logic;
iwb_stb_o : out std_logic;
iwb_sel_o : out std_logic_vector(3 downto 0);
iwb_we_o : out std_logic;
iwb_ack_i : in std_logic;
dwb_adr_o : out std_logic_vector(g_addr_width-1 downto 0);
......@@ -27,7 +29,20 @@ entity wrc_lm32 is
dwb_stb_o : out std_logic;
dwb_sel_o : out std_logic_vector(3 downto 0);
dwb_we_o : out std_logic;
dwb_ack_i : in std_logic
dwb_ack_i : in std_logic;
jwb_adr_i : in std_logic_vector(g_addr_width-1 downto 0);
jwb_dat_i : in std_logic_vector(31 downto 0);
jwb_dat_o : out std_logic_vector(31 downto 0);
jwb_cyc_i : in std_logic;
jwb_stb_i : in std_logic;
jwb_sel_i : in std_logic_vector(3 downto 0);
jwb_we_i : in std_logic;
jwb_ack_o : out std_logic;
trace_pc_o: out std_logic_vector(31 downto 0);
trace_pc_valid_o: out std_logic;
trace_eret_o:out std_logic
);
end wrc_lm32;
......@@ -42,6 +57,12 @@ architecture rtl of wrc_lm32 is
I_ACK_I : in std_logic;
I_ERR_I : in std_logic;
I_RTY_I : in std_logic;
J_DAT_I : in std_logic_vector(31 downto 0);
J_ADR_I : in std_logic_vector(31 downto 0);
J_CYC_I : in std_logic;
J_SEL_I : in std_logic_vector(3 downto 0);
J_STB_I : in std_logic;
J_WE_I : in std_logic;
D_DAT_I : in std_logic_vector(31 downto 0);
D_ACK_I : in std_logic;
D_ERR_I : in std_logic;
......@@ -55,6 +76,8 @@ architecture rtl of wrc_lm32 is
I_CTI_O : out std_logic_vector(2 downto 0);
I_LOCK_O : out std_logic;
I_BTE_O : out std_logic_vector(1 downto 0);
J_ACK_O : out std_logic;
J_DAT_O : out std_logic_vector(31 downto 0);
D_DAT_O : out std_logic_vector(31 downto 0);
D_ADR_O : out std_logic_vector(31 downto 0);
D_CYC_O : out std_logic;
......@@ -63,16 +86,20 @@ architecture rtl of wrc_lm32 is
D_WE_O : out std_logic;
D_CTI_O : out std_logic_vector(2 downto 0);
D_LOCK_O : out std_logic;
D_BTE_O : out std_logic_vector(1 downto 0));
D_BTE_O : out std_logic_vector(1 downto 0);
trace_pc_o : out std_logic_vector(31 downto 0);
trace_pc_valid_o : out std_logic;
trace_eret_o: out std_logic);
end component lm32_top;
signal rst : std_logic;
signal iwb_adr_int : std_logic_vector(31 downto 0);
signal dwb_adr_int : std_logic_vector(31 downto 0);
signal jwb_adr_int : std_logic_vector(31 downto 0);
signal irqs_vec : std_logic_vector(31 downto 0);
signal dwb_data_int : std_logic_vector(31 downto 0);
begin
irqs_vec(g_num_irqs-1 downto 0) <= irq_i;
......@@ -90,6 +117,12 @@ begin
I_ACK_I => iwb_ack_i,
I_ERR_I => '0',
I_RTY_I => '0',
J_DAT_I => jwb_dat_i,
J_ADR_I => jwb_adr_int,
J_CYC_I => jwb_cyc_i,
J_SEL_I => jwb_sel_i,
J_STB_I => jwb_stb_i,
J_WE_I => jwb_we_i,
D_DAT_I => dwb_data_int,
D_ACK_I => dwb_ack_i,
D_ERR_I => '0',
......@@ -97,12 +130,14 @@ begin
I_DAT_O => iwb_dat_o,