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White Rabbit core collection
Commit ad01cd09 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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board/svec: added DMTD clock output

parent 3dcac448
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Showing with 10 additions and 2 deletions
board/svec/wr_svec_pkg.vhd
View file @ ad01cd09
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch> -- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16 -- Created : 2017-02-16
-- Last update: 2019-04-23 -- Last update: 2019-09-25
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN -- Copyright (c) 2017 CERN
...@@ -73,6 +73,7 @@ package wr_svec_pkg is ...@@ -73,6 +73,7 @@ package wr_svec_pkg is
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0'; clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0'; pps_ext_i : in std_logic := '0';
clk_dmtd_125m_o : out std_logic;
clk_sys_62m5_o : out std_logic; clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic; clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic_vector(3 downto 0); clk_pll_aux_o : out std_logic_vector(3 downto 0);
......
board/svec/xwrc_board_svec.vhd
View file @ ad01cd09
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch> -- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16 -- Created : 2017-02-16
-- Last update: 2019-04-23 -- Last update: 2019-09-25
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules -- Description: Top-level wrapper for WR PTP core including all the modules
...@@ -107,6 +107,8 @@ entity xwrc_board_svec is ...@@ -107,6 +107,8 @@ entity xwrc_board_svec is
clk_sys_62m5_o : out std_logic; clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output -- 125MHz ref clock output
clk_ref_125m_o : out std_logic; clk_ref_125m_o : out std_logic;
-- 125.x MHz DDMTD clock
clk_dmtd_125m_o : out std_logic;
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE -- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o : out std_logic_vector(3 downto 0); clk_pll_aux_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to clk_pll_aux_o clocks -- active low reset outputs, synchronous to clk_pll_aux_o clocks
...@@ -278,6 +280,9 @@ architecture struct of xwrc_board_svec is ...@@ -278,6 +280,9 @@ architecture struct of xwrc_board_svec is
signal clk_10m_ext : std_logic; signal clk_10m_ext : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0); signal clk_pll_aux : std_logic_vector(3 downto 0);
attribute keep : string;
attribute keep of clk_pll_dmtd : signal is "TRUE";
-- Reset logic -- Reset logic
signal areset_edge_ppulse : std_logic; signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic; signal rst_62m5_n : std_logic;
...@@ -549,4 +554,6 @@ begin -- architecture struct ...@@ -549,4 +554,6 @@ begin -- architecture struct
onewire_in(0) <= onewire_i; onewire_in(0) <= onewire_i;
onewire_in(1) <= '1'; onewire_in(1) <= '1';
clk_dmtd_125m_o <= clk_pll_dmtd;
end architecture struct; end architecture struct;
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