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White Rabbit core collection
Commit ab824629 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore_v2: testbenches from wishbonized

parent 9cb82351
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testbench/mini_bone/Manifest.py 0 → 100644
View file @ ab824629
action = "simulation"
files = "main.sv"
fetchto = "../../../ip_cores"
vlog_opt="+incdir+../../sim"
modules ={"local" : ["../../modules/mini_bone",
"../../" ] };
testbench/mini_bone/main.sv 0 → 100644
View file @ ab824629
/* Some basic definitions: types, abstract BusAccessor class */
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
module main;
wire m_cyc,m_we,m_stb;
wire[3:0]m_sel;
wire[31:0]m_adr,m_wrdat;
logic [31:0] m_rddat;
logic m_ack;
/* clock & reset generator */
reg clk_sys = 1'b0;
reg rst_n = 1'b0;
always #5ns clk_sys <= ~clk_sys;
initial begin
repeat(3) @(posedge clk_sys);
rst_n <= 1'b1;
end
/* A wishbone master, sending the packets to the MiniBone.
Controlled via child CWishboneAccessor object. */
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_source
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
/* A Wishbone slave. Receives the packets produced by the MiniBone. */
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_sink
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
mini_bone
#(
.g_class_mask(8'hff),
.g_our_ethertype('ha0a0))
DUT
(
.clk_sys_i (clk_sys),
.rst_n_i (rst_n),
/* Packet I/O - from the Endpoint to the MB */
.snk_cyc_i (U_source.master.cyc),
.snk_stb_i (U_source.master.stb),
.snk_dat_i (U_source.master.dat_o),
.snk_sel_i (U_source.master.sel),
.snk_adr_i (U_source.master.adr),
.snk_we_i (U_source.master.we),
.snk_stall_o(U_source.master.stall),
.snk_ack_o (U_source.master.ack),
/* Packet I/O - from the MB to the Endpoint */
.src_cyc_o (U_sink.slave.cyc),
.src_stb_o (U_sink.slave.stb),
.src_dat_o (U_sink.slave.dat_i),
.src_adr_o (U_sink.slave.adr),
.src_sel_o (U_sink.slave.sel),
.src_we_o (U_sink.slave.we),
.src_ack_i (U_sink.slave.ack),
.src_stall_i (U_sink.slave.stall),
/* WB Master driving the memory */
.master_cyc_o (m_cyc),
.master_we_o (m_we),
.master_stb_o (m_stb),
.master_sel_o (m_sel),
.master_adr_o (m_adr),
.master_dat_o (m_wrdat),
.master_dat_i (m_rddat),
.master_ack_i (m_ack));
logic [31:0] mem[65536];
/* a trivial wishbone memory model */
always@(posedge clk_sys)
if(!rst_n) begin
m_ack <= 0;
m_rddat <= 0;
end else begin
if(m_ack)
m_ack <= 0;
else if(m_cyc && m_stb) begin
if(m_we)
begin
/* $display("MemWrite: addr %x data %x", m_adr, m_wrdat); */
mem[m_adr[15:0]] <= m_wrdat;
end
m_rddat <= mem[m_adr[15:0]];
m_ack <= 1;
end
end
/* Packet Source and Sink objects - these objects translate Ethernet packets into/from
Wishbone bus transactions, extracting the statuses and OOB */
WBPacketSource src;
WBPacketSink sink;
/* Executes a write cycle using minibone */
task mbone_write(uint32_t addr, uint32_t data);
EthPacket pkt;
pkt = new;
/* some dummy addresses */
pkt.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
pkt.src = '{1,2,3,4,5,6};
pkt.ethertype = 'ha0a0;
/* set the payload size to the minimum acceptable value:
(46 bytes payload + 14 bytes header + 4 bytes CRC) */
pkt.set_size(46);
/* .. and fill in the packet structure */
pkt.payload[0] = 0;
pkt.payload[1] = 'h1f; /* Flags (write = 1, SEL = 0xf) */
pkt.payload[2] = (addr >> 24) & 'hff;
pkt.payload[3] = (addr >> 16) & 'hff;
pkt.payload[4] = (addr >> 8) & 'hff;
pkt.payload[5] = (addr >> 0) & 'hff;
pkt.payload[6] = (data >> 24) & 'hff;
pkt.payload[7] = (data >> 16) & 'hff;
pkt.payload[8] = (data >> 8) & 'hff;
pkt.payload[9] = (data >> 0) & 'hff;
/* send the packet */
src.send(pkt);
/* and receive the reply. No error handling yet. */
sink.recv(pkt);
endtask // mbone_write
/* The same thing, but for reads */
task mbone_read(uint32_t addr, output uint32_t data);
EthPacket pkt;
pkt = new;
pkt.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
pkt.src = '{1,2,3,4,5,6};
pkt.ethertype = 'ha0a0;
pkt.set_size(46);
pkt.payload[0] = 0;
pkt.payload[1] = 'h0f;
pkt.payload[2] = (addr >> 24) & 'hff;
pkt.payload[3] = (addr >> 16) & 'hff;
pkt.payload[4] = (addr >> 8) & 'hff;
pkt.payload[5] = (addr >> 0) & 'hff;
src.send(pkt);
sink.recv(pkt);
// pkt.dump();
if((pkt.payload[1] & 3) == 1)
begin
reg[31:0] d;
d[31:24] = pkt.payload[2];
d[23:16] = pkt.payload[3];
d[15:8] = pkt.payload[4];
d[7:0] = pkt.payload[5];
data = d;
end
endtask // mbone_read
initial begin
int i, retries;
uint32_t rval;
int seed;
#1us;
/* Create the sink/source objects - they communicate with the WB Master/Slave using an Accessor
object:
Ethernet Packet (eth_packet_t) -> src->send() -> serialization -> sequence of reads/writes -> accessor -> IWishboneMaster -> device under test */
src = new(U_source.get_accessor());
sink = new(U_sink.get_accessor());
/* Make the things not ideal */
U_source.settings.throttle_prob = 0.1;
U_source.settings.gen_random_throttling = 1; /* 10% probability of STB going low */
U_sink.settings.stall_prob = 0.1;
U_sink.settings.gen_random_stalls = 1; /* 10 % probability of STALL event, stalls 1-3 cycles long */
U_sink.settings.stall_min_duration = 1;
U_sink.settings.stall_max_duration = 3;
/* try executing a bunch of random writes and verify if the written data is where it should be */
for(retries = 0; retries <10; retries++)
begin
const int n_writes = 100;
$display("Iteration %d", retries);
seed = retries;
for(i=0;i<n_writes;i++)
mbone_write(i, $dist_uniform(seed, 0, (1<<31)-1));
seed = retries;
for(i=0;i<n_writes;i++)
begin
mbone_read(i, rval);
if(rval != $dist_uniform(seed, 0, (1<<31)-1))
begin
$error("Inconsistency at %d", i);
$stop;
end
end
end
$display("Test passed");
$stop;
end
endmodule // main
testbench/mini_bone/run.do 0 → 100644
View file @ ab824629
make
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 10ms
wave zoomfull
radix -hexadecimal
testbench/mini_bone/wave.do 0 → 100644
View file @ ab824629
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_class_mask
add wave -noupdate /main/DUT/g_our_ethertype
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/snk_cyc_i
add wave -noupdate /main/DUT/snk_stb_i
add wave -noupdate /main/DUT/snk_sel_i
add wave -noupdate /main/DUT/snk_adr_i
add wave -noupdate /main/DUT/snk_dat_i
add wave -noupdate /main/DUT/snk_we_i
add wave -noupdate /main/DUT/snk_stall_o
add wave -noupdate /main/DUT/snk_ack_o
add wave -noupdate /main/DUT/snk_err_o
add wave -noupdate /main/DUT/src_cyc_o
add wave -noupdate /main/DUT/src_stb_o
add wave -noupdate /main/DUT/src_dat_o
add wave -noupdate /main/DUT/src_adr_o
add wave -noupdate /main/DUT/src_we_o
add wave -noupdate /main/DUT/src_ack_i
add wave -noupdate /main/DUT/src_err_i
add wave -noupdate /main/DUT/src_sel_o
add wave -noupdate /main/DUT/src_stall_i
add wave -noupdate /main/DUT/master_cyc_o
add wave -noupdate /main/DUT/master_we_o
add wave -noupdate /main/DUT/master_stb_o
add wave -noupdate /main/DUT/master_sel_o
add wave -noupdate /main/DUT/master_adr_o
add wave -noupdate /main/DUT/master_dat_o
add wave -noupdate /main/DUT/master_dat_i
add wave -noupdate /main/DUT/master_ack_i
add wave -noupdate /main/DUT/src_out
add wave -noupdate /main/DUT/src_in
add wave -noupdate /main/DUT/snk_out
add wave -noupdate /main/DUT/snk_in
add wave -noupdate /main/DUT/master_out
add wave -noupdate /main/DUT/master_in
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {67408050000 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {125312500 ps} {256562500 ps}
testbench/wbp_mux/Manifest.py 0 → 100644
View file @ ab824629
action = "simulation"
files = "main.sv"
#fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim"
modules ={"local" : ["../../ip_cores/general-cores",
"../../modules/wr_endpoint",
"../../modules/wr_mini_nic",
"../../modules/wrc_core" ] };
testbench/wbp_mux/main.sv 0 → 100644
View file @ ab824629
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "if_wb_link.svh"
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`define WIRE_WB_SINK(iface, prefix) \
.prefix``_adr_i(iface.adr), \
.prefix``_dat_i(iface.dat_o), \
.prefix``_stb_i(iface.stb), \
.prefix``_sel_i(iface.sel), \
.prefix``_cyc_i(iface.cyc), \
.prefix``_ack_o(iface.ack), \
.prefix``_err_o(iface.err), \
.prefix``_stall_o(iface.stall)
`define WIRE_WB_SOURCE(iface, prefix) \
.prefix``_adr_o(iface.adr), \
.prefix``_dat_o(iface.dat_i), \
.prefix``_stb_o(iface.stb), \
.prefix``_sel_o(iface.sel), \
.prefix``_cyc_o(iface.cyc), \
.prefix``_ack_i(iface.ack), \
.prefix``_err_i(iface.err), \
.prefix``_stall_i(iface.stall)
module mux_svwrap
(
input clk_sys_i,
input rst_n_i
);
IWishboneMaster #(2,16) U_ep_src (clk_sys_i, rst_n_i);
IWishboneMaster #(2,16) U_minic_src (clk_sys_i, rst_n_i);
IWishboneMaster #(2,16) U_ext_src (clk_sys_i, rst_n_i);
IWishboneSlave #(2,16) U_ep_snk (clk_sys_i, rst_n_i);
IWishboneSlave #(2,16) U_minic_snk (clk_sys_i, rst_n_i);
IWishboneSlave #(2,16) U_ext_snk (clk_sys_i, rst_n_i);
wbp_mux
U_Mux
(
.clk_sys_i (clk_sys_i),
.rst_n_i (rst_n_i),
`WIRE_WB_SINK(U_ep_src, ep_wbs),
`WIRE_WB_SOURCE(U_ep_snk, ep_wbm),
`WIRE_WB_SINK(U_minic_src, ptp_wbs),
`WIRE_WB_SOURCE(U_minic_snk, ptp_wbm),
`WIRE_WB_SINK(U_ext_src, ext_wbs),
`WIRE_WB_SOURCE(U_ext_snk, ext_wbm),
.class_core_i (8'hf0)
);
assign U_ep_snk.we = 1;
assign U_minic_snk.we = 1;
assign U_ext_snk.we = 1;
WBPacketSource ep_src, minic_src, ext_src;
WBPacketSink ep_snk, minic_snk, ext_snk;
initial begin
@(posedge rst_n_i);
@(posedge clk_sys_i);
ep_src = new(U_ep_src.get_accessor());
minic_src = new(U_minic_src.get_accessor());
ext_src = new(U_ext_src.get_accessor());
ep_snk = new(U_ep_snk.get_accessor());
minic_snk = new(U_minic_snk.get_accessor());
ext_snk = new(U_ext_snk.get_accessor());
end
endmodule // mux_svwrap
module main;
reg clk_ref = 1'b0;
wire clk_sys ;
reg rst_n = 1'b0;
always #4ns clk_ref <= ~clk_ref;
assign clk_sys = clk_ref;
initial begin
repeat(3) @(posedge clk_sys);
rst_n <= 1'b1;
end
mux_svwrap DUT (clk_sys, rst_n);
task verify_rx_queue(WBPacketSink snk, EthPacket q[$], output int n_packets);
automatic int n;
n =0;
while(snk.poll())
begin
EthPacket from_q, pkt;
n++;
snk.recv(pkt);
from_q = q.pop_front();
if(!pkt.equal(from_q))
begin
pkt.dump();
from_q.dump(); $stop;
end
end
n_packets = n;
endtask // verify_rx_queue
task automatic send_random_packets(WBPacketSource src,ref EthPacket q[$], input int n_packets, input int pclass);
EthPacket pkt, tmpl;
EthPacketGenerator gen = new;
int i;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{10,11,12,13,14,15};
tmpl.has_smac = 1;
tmpl.is_q = 0;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(46, 1000);
for(i=0;i<n_packets;i++)
begin
pkt = gen.gen();
pkt.pclass = pclass;
q.push_back(pkt);
src.send(pkt);
end
endtask // send_random_packets
task test_classifier(int n_packets);
int i, seed = 0,n1=0,n2=0;
EthPacket pkt, tmpl;
EthPacket to_ext[$], to_minic[$];
EthPacketGenerator gen = new;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{10,11,12,13,14,15};
tmpl.has_smac = 1;
tmpl.is_q = 0;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(46, 1000);
for(i=0;i<n_packets;i++)
begin
pkt = gen.gen();
pkt.pclass = (1<<$dist_uniform(seed,0,7));
if(pkt.pclass & 'hf0)
to_minic.push_back(pkt);
else
to_ext.push_back(pkt);
DUT.ep_src.send(pkt);
end
verify_rx_queue(DUT.ext_snk, to_ext, n1);
verify_rx_queue(DUT.minic_snk, to_minic, n2);
if(n1+n2 != n_packets)
$error("FAILURE n1 %d n2 %d n_packets %d", n1, n2, n_packets);
else
$display("PASS");
endtask // test_classifier
task automatic test_arbiter(int n_packets);
int n, n1, n2;
EthPacket from_ext[$], from_minic[$], pkt;
n = 0;
n1 = 0;
n2 = 0;
fork
send_random_packets(DUT.ext_src, from_ext, n_packets, 1);
send_random_packets(DUT.minic_src, from_minic, n_packets, 2);
join
while(DUT.ep_snk.poll())
begin
EthPacket from_q;
DUT.ep_snk.recv(pkt);
if(pkt.pclass == 1)
begin
from_q = from_ext.pop_front();
n1++;
end
else
begin
from_q = from_minic.pop_front();
n2++;
end
if(!from_q.equal(pkt))
begin
from_q.dump();
pkt.dump();
$error("FAIL at %d (%d,%d)\n", n,n1,n2);
break;
end
n++;
end // while (DUT.ep_snk.poll())
$display("PASS");
endtask // test_arbiter
initial begin
int i;
EthPacket pkt, tmpl;
EthPacketGenerator gen = new;
@(posedge rst_n);
@(posedge clk_sys);
test_classifier(100);
// test_arbiter(10000);
end
endmodule // main
testbench/wbp_mux/run.do 0 → 100644
View file @ ab824629
vlog -sv main.sv +incdir+"." +incdir+../../sim
make -f Makefile
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 250us
wave zoomfull
radix -hexadecimal
testbench/wbp_mux/wave.do 0 → 100644
View file @ ab824629
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_Mux/clk_sys_i
add wave -noupdate /main/DUT/U_Mux/rst_n_i
add wave -noupdate /main/DUT/U_Mux/class_core_i
add wave -divider ENDPOINT
add wave -noupdate /main/DUT/U_Mux/ep_wbs_adr_i
add wave -noupdate /main/DUT/U_Mux/ep_wbs_dat_i
add wave -noupdate /main/DUT/U_Mux/ep_wbs_sel_i
add wave -noupdate /main/DUT/U_Mux/ep_wbs_cyc_i
add wave -noupdate /main/DUT/U_Mux/ep_wbs_stb_i
add wave -noupdate /main/DUT/U_Mux/ep_wbs_ack_o
add wave -noupdate /main/DUT/U_Mux/ep_wbs_err_o
add wave -noupdate /main/DUT/U_Mux/ep_wbs_stall_o
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_adr_o
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_dat_o
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_sel_o
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_cyc_o
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_stb_o
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_ack_i
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_err_i
#add wave -noupdate /main/DUT/U_Mux/ep_wbm_stall_i
add wave -divider MiNIC
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_adr_i
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_dat_i
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_sel_i
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_cyc_i
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_stb_i
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_ack_o
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_err_o
#add wave -noupdate /main/DUT/U_Mux/ptp_wbs_stall_o
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_adr_o
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_dat_o
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_sel_o
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_cyc_o
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_stb_o
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_ack_i
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_err_i
add wave -noupdate /main/DUT/U_Mux/ptp_wbm_stall_i
add wave -divider EXT
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_adr_i
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_dat_i
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_sel_i
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_cyc_i
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_stb_i
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_ack_o
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_err_o
#add wave -noupdate /main/DUT/U_Mux/ext_wbs_stall_o
add wave -noupdate /main/DUT/U_Mux/ext_wbm_adr_o
add wave -noupdate /main/DUT/U_Mux/ext_wbm_dat_o
add wave -noupdate /main/DUT/U_Mux/ext_wbm_sel_o
add wave -noupdate /main/DUT/U_Mux/ext_wbm_cyc_o
add wave -noupdate /main/DUT/U_Mux/ext_wbm_stb_o
add wave -noupdate /main/DUT/U_Mux/ext_wbm_ack_i
add wave -noupdate /main/DUT/U_Mux/ext_wbm_err_i
add wave -noupdate /main/DUT/U_Mux/ext_wbm_stall_i
add wave -divider MUX
#add wave -noupdate /main/DUT/U_Mux/mux
#add wave -noupdate /main/DUT/U_Mux/mux_last
#add wave -noupdate /main/DUT/U_Mux/mux_extdat_reg
#add wave -noupdate /main/DUT/U_Mux/mux_ptpdat_reg
#add wave -noupdate /main/DUT/U_Mux/mux_extadr_reg
#add wave -noupdate /main/DUT/U_Mux/mux_ptpadr_reg
#add wave -noupdate /main/DUT/U_Mux/mux_extsel_reg
#add wave -noupdate /main/DUT/U_Mux/mux_ptpsel_reg
#add wave -noupdate /main/DUT/U_Mux/mux_extcyc_reg
#add wave -noupdate /main/DUT/U_Mux/mux_ptpcyc_reg
#add wave -noupdate /main/DUT/U_Mux/mux_extstb_reg
#add wave -noupdate /main/DUT/U_Mux/mux_ptpstb_reg
#add wave -noupdate /main/DUT/U_Mux/mux_pend_ext
#add wave -noupdate /main/DUT/U_Mux/mux_pend_ptp
#add wave -noupdate /main/DUT/U_Mux/force_stall
add wave -noupdate /main/DUT/U_Mux/demux
add wave -noupdate /main/DUT/U_Mux/dmux_stall_mask
add wave -noupdate /main/DUT/U_Mux/dmux_status_reg
add wave -noupdate /main/DUT/U_Mux/ep_stall_mask
add wave -noupdate /main/DUT/U_Mux/ptp_select
add wave -noupdate /main/DUT/U_Mux/ext_select
add wave -noupdate /main/DUT/U_Mux/ptp_send_status
add wave -noupdate /main/DUT/U_Mux/ext_send_status
add wave -noupdate /main/DUT/U_Mux/dmux_status_class
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {50325670 fs} 0}
configure wave -namecolwidth 350
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {262500 ns}
testbench/wr_endpoint/full_tb/endpoint_phy_wrapper.svh
View file @ ab824629
...@@ -38,8 +38,8 @@ module endpoint_phy_wrapper ...@@ -38,8 +38,8 @@ module endpoint_phy_wrapper
generate generate
if(g_phy_type == "TBI") begin if(g_phy_type == "TBI") begin
assign rx_clock = clk_rx_i; assign rx_clock = clk_ref_i;
assign tx_clock = clk_ref_i; assign tx_clock = clk_rx_i;
wr_tbi_phy U_Phy wr_tbi_phy U_Phy
...@@ -61,11 +61,11 @@ module endpoint_phy_wrapper ...@@ -61,11 +61,11 @@ module endpoint_phy_wrapper
.serdes_rx_bitslide_o (grx_bitslide), .serdes_rx_bitslide_o (grx_bitslide),
.tbi_refclk_i (clk_ref_new), .tbi_refclk_i (clk_ref_i),
.tbi_rbclk_i (clk_ref_old), .tbi_rbclk_i (clk_rx_i),
.tbi_td_o (n2o), .tbi_td_o (td_o),
.tbi_rd_i (o2n), .tbi_rd_i (rd_i),
.tbi_syncen_o (), .tbi_syncen_o (),
.tbi_loopen_o (), .tbi_loopen_o (),
.tbi_prbsen_o (), .tbi_prbsen_o (),
...@@ -112,7 +112,7 @@ module endpoint_phy_wrapper ...@@ -112,7 +112,7 @@ module endpoint_phy_wrapper
.g_with_rx_buffer(0), .g_with_rx_buffer(0),
.g_with_timestamper (1), .g_with_timestamper (1),
.g_with_dmtd (0), .g_with_dmtd (0),
.g_with_dpi_classifier (0), .g_with_dpi_classifier (1),
.g_with_vlans (0), .g_with_vlans (0),
.g_with_rtu (0) .g_with_rtu (0)
) DUT ( ) DUT (
...@@ -147,6 +147,7 @@ module endpoint_phy_wrapper ...@@ -147,6 +147,7 @@ module endpoint_phy_wrapper
.src_we_o (snk.we), .src_we_o (snk.we),
.src_stall_i (snk.stall), .src_stall_i (snk.stall),
.src_ack_i (snk.ack), .src_ack_i (snk.ack),
.src_err_i(1'b0),
.snk_dat_i (src.dat_o[15:0]), .snk_dat_i (src.dat_o[15:0]),
.snk_adr_i (src.adr[1:0]), .snk_adr_i (src.adr[1:0]),
...@@ -179,7 +180,7 @@ module endpoint_phy_wrapper ...@@ -179,7 +180,7 @@ module endpoint_phy_wrapper
.wb_stb_i (sys.stb), .wb_stb_i (sys.stb),
.wb_we_i (sys.we), .wb_we_i (sys.we),
.wb_sel_i(sys.sel), .wb_sel_i(sys.sel),
.wb_adr_i(sys.adr[5:0]), .wb_adr_i(sys.adr[7:0]),
.wb_dat_i(sys.dat_o), .wb_dat_i(sys.dat_o),
.wb_dat_o(sys.dat_i), .wb_dat_o(sys.dat_i),
.wb_ack_o (sys.ack) .wb_ack_o (sys.ack)
......
testbench/wr_endpoint/full_tb/main.sv
View file @ ab824629
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
class CSimDrv_WR_Endpoint; class CSimDrv_WR_Endpoint;
protected CBusAccessor m_acc; protected CBusAccessor m_acc;
...@@ -51,7 +52,32 @@ class CSimDrv_WR_Endpoint; ...@@ -51,7 +52,32 @@ class CSimDrv_WR_Endpoint;
task pfilter_enable(int enable); task pfilter_enable(int enable);
m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0); m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0);
endtask endtask // pfilter_enable
task automatic mdio_read(int base, int addr, output int val);
reg[31:0] rval;
m_acc.write(base+`ADDR_EP_MDIO_CR, (addr>>2) << 16);
while(1)begin
m_acc.read(base+`ADDR_EP_MDIO_SR, rval);
if(rval[31]) begin
val = rval[15:0];
return;
end
end
endtask // mdio_read
task automatic mdio_write(int base, int addr,int val);
reg[31:0] rval;
m_acc.write(base+`ADDR_EP_MDIO_CR, (addr>>2) << 16 | `EP_MDIO_CR_RW);
while(1)begin
m_acc.read(base+`ADDR_EP_MDIO_SR, rval);
if(rval[31])
return;
end
endtask // automatic
endclass // CSimDrv_WR_Endpoint endclass // CSimDrv_WR_Endpoint
...@@ -113,22 +139,31 @@ module main; ...@@ -113,22 +139,31 @@ module main;
); );
wire rxn,rxp,txn,txp; wire rxn,rxp,txn,txp;
wire [9:0] td;
wire [9:0] rd;
old_endpoint_test_wrapper old_endpoint_test_wrapper
#( #(
.g_phy_type("GTP")) .g_phy_type("TBI"))
U_oldep_wrap U_oldep_wrap
( (
.clk_sys_i(clk_sys), .clk_sys_i(clk_sys),
.clk_ref_i(clk_ref_old), .clk_ref_i(clk_ref_old),
.clk_rx_i(clk_ref_new), .clk_rx_i(clk_ref_new),
.rst_n_i(rst_n), .rst_n_i(rst_n),
.td_o(td),
.rd_i(rd)
/* -----\/----- EXCLUDED -----\/-----
.rxp_i(rxp), .rxp_i(rxp),
.rxn_i(rxn), .rxn_i(rxn),
.txp_o(txp), .txp_o(txp),
.txn_o(txn) .txn_o(txn)
-----/\----- EXCLUDED -----/\----- */
); );
reg clk_ref_gtx = 1; reg clk_ref_gtx = 1;
...@@ -137,22 +172,28 @@ module main; ...@@ -137,22 +172,28 @@ module main;
endpoint_phy_wrapper endpoint_phy_wrapper
#( #(
.g_phy_type("GTX")) .g_phy_type("TBI"))
U_Wrapped_EP U_Wrapped_EP
( (
.clk_sys_i(clk_sys), .clk_sys_i(clk_sys),
.clk_ref_i(clk_ref_new), .clk_ref_i(clk_ref_new),
.clk_rx_i(clk_ref_new),
.rst_n_i(rst_n), .rst_n_i(rst_n),
.snk (U_wrf_sink.slave), .snk (U_wrf_sink.slave),
.src(U_wrf_source.master), .src(U_wrf_source.master),
.sys(U_sys_bus_master.master), .sys(U_sys_bus_master.master),
.td_o(rd),
.rd_i(td)
/* -----\/----- EXCLUDED -----\/-----
.txn_o(rxn), .txn_o(rxn),
.txp_o(rxp), .txp_o(rxp),
.rxn_i(txn), .rxn_i(txn),
.rxp_i(txp) .rxp_i(txp)
-----/\----- EXCLUDED -----/\----- */
); );
...@@ -204,12 +245,13 @@ module main; ...@@ -204,12 +245,13 @@ module main;
tmpl = new; tmpl = new;
tmpl.src = '{1,2,3,4,5,6}; tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{10,11,12,13,14,15}; tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
tmpl.has_smac = 1; tmpl.has_smac = 1;
tmpl.is_q = is_q; tmpl.is_q = is_q;
tmpl.vid = 100; tmpl.vid = 100;
tmpl.ethertype = 'h88f7;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE/* | EthPacketGenerator::TX_OOB*/) ; //
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
gen.set_template(tmpl); gen.set_template(tmpl);
gen.set_size(64,1500); gen.set_size(64,1500);
...@@ -245,23 +287,30 @@ module main; ...@@ -245,23 +287,30 @@ module main;
task init_pfilter(CSimDrv_WR_Endpoint ep_drv); task init_pfilter(CSimDrv_WR_Endpoint ep_drv);
PFilterMicrocode mc = new; PFilterMicrocode mc = new;
mc.cmp(0, 'h0a0b, 'hffff, PFilterMicrocode::MOV, 1); mc.cmp(0, 'hffff, 'hffff, PFilterMicrocode::MOV, 1);
mc.cmp(1, 'h0c0a, 'hffff, PFilterMicrocode::AND, 1); mc.cmp(1, 'hffff, 'hffff, PFilterMicrocode::AND, 1);
mc.cmp(2, 'h0e0f, 'hffff, PFilterMicrocode::AND, 1); mc.cmp(2, 'hffff, 'hffff, PFilterMicrocode::AND, 1);
mc.logic2(2, 1, PFilterMicrocode::MOV, 0); mc.cmp(0, 'h011b, 'hffff, PFilterMicrocode::MOV, 2);
mc.cmp(3, 'h0102, 'hffff, PFilterMicrocode::MOV, 1); mc.cmp(1, 'h1900, 'hffff, PFilterMicrocode::AND, 2);
mc.cmp(4, 'h030a, 'hffff, PFilterMicrocode::AND, 1); mc.cmp(2, 'h0000, 'hffff, PFilterMicrocode::AND, 2);
mc.cmp(5, 'h0506, 'hffff, PFilterMicrocode::AND, 1); mc.cmp(0, 'h0050, 'hffff, PFilterMicrocode::MOV, 3);
mc.logic2(3, 1, PFilterMicrocode::MOV, 0); mc.cmp(1, 'hcafe, 'hffff, PFilterMicrocode::AND, 3);
mc.cmp(6,'h86ba, 'hffff, PFilterMicrocode::MOV, 4); mc.cmp(2, 'hbabe, 'hffff, PFilterMicrocode::AND, 3);
mc.cmp(6, 'ha0a0, 'hffff, PFilterMicrocode::MOV, 4);
mc.logic3(5, 2, PFilterMicrocode::AND, 3, PFilterMicrocode::OR, 4); mc.cmp(6, 'h88f7, 'hffff, PFilterMicrocode::MOV, 5);
mc.logic3(7, 3, PFilterMicrocode::AND, 4, PFilterMicrocode::OR, 5);
mc.logic2(23, 7, PFilterMicrocode::NOT, 0);
mc.logic2(31, 3, PFilterMicrocode::AND, 4);
mc.logic2(24, 5, PFilterMicrocode::MOV, 0);
ep_drv.pfilter_load_microcode(mc.assemble()); ep_drv.pfilter_load_microcode(mc.assemble());
ep_drv.pfilter_enable(1); ep_drv.pfilter_enable(1);
endtask // init_pfilter endtask // init_pfilter
initial begin initial begin
CWishboneAccessor sys_bus; CWishboneAccessor sys_bus;
WBPacketSource src = new(U_wrf_source.get_accessor()); WBPacketSource src = new(U_wrf_source.get_accessor());
...@@ -326,8 +375,10 @@ module main; ...@@ -326,8 +375,10 @@ module main;
begin begin
$display("RX Iter %d", i); $display("RX Iter %d", i);
tx_test(5, 0, 0, o_src, sink); tx_test(5, 0, 0, o_src, sink);
/* -----\/----- EXCLUDED -----\/-----
$display("TX Iter %d", i); $display("TX Iter %d", i);
tx_test(5, 0, 0, src, o_sink); tx_test(5, 0, 0, src, o_sink);
-----/\----- EXCLUDED -----/\----- */
end end
end // initial begin end // initial begin
......
testbench/wr_endpoint/full_tb/wave.do
View file @ ab824629
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /main/clk_sys add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/dreq_pipe
add wave -noupdate /main/clk_ref add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/fab_pipe
add wave -noupdate /main/clk_tdc add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/src_wb_o
add wave -noupdate /main/rst_n add wave -noupdate /main/U_Wrapped_EP/DUT/U_Rx_Path/src_wb_i
add wave -noupdate /main/trig_a
add wave -noupdate /main/trig_cal
add wave -noupdate /main/acam_wr_n
add wave -noupdate /main/acam_cs_n
add wave -noupdate /main/acam_rd_n
add wave -noupdate /main/acam_oe_n
add wave -noupdate /main/acam_adr
add wave -noupdate /main/acam_data
add wave -noupdate /main/tdc_d_o
add wave -noupdate /main/tdc_d_oe
add wave -noupdate /main/acam_start_dis
add wave -noupdate /main/acam_stop_dis
add wave -noupdate /main/acam_alutrigger
add wave -noupdate /main/trig_a_n_delayed
add wave -noupdate /main/tdc_start_delayed
add wave -noupdate /main/wr_utc
add wave -noupdate /main/wr_coarse
add wave -noupdate /main/wr_time_valid
add wave -noupdate /main/tdc_start_div
add wave -noupdate /main/tdc_start
add wave -noupdate /main/wr_time_valid_d0
add wave -noupdate /main/acam_ef1
add wave -noupdate /main/delay_len
add wave -noupdate /main/delay_pulse
add wave -noupdate /main/delay_val
add wave -noupdate /main/d_out
add wave -noupdate /main/spi_loop
add wave -noupdate /main/c_coarse_range
add wave -noupdate /main/fd_drv
add wave -noupdate /main/wb
add wave -noupdate /main/prev
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {20442364860 fs} 0} WaveRestoreCursors {{Cursor 1} {199349192100 fs} 0}
configure wave -namecolwidth 413 configure wave -namecolwidth 413
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -51,4 +20,4 @@ configure wave -griddelta 40 ...@@ -51,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 fs} {6754054050 fs} WaveRestoreZoom {0 fs} {262500 ns}
testbench/wr_minic_with_ep/ep2ep_wrapper.svh
View file @ ab824629
...@@ -191,7 +191,7 @@ module ep2ep_wrapper ...@@ -191,7 +191,7 @@ module ep2ep_wrapper
.phy_rx_enc_err_i (1'b0), .phy_rx_enc_err_i (1'b0),
.phy_rx_bitslide_i (5'b0), .phy_rx_bitslide_i (5'b0),
.src_dat_o (src_b.dat_i), .src_dat_o (src_b.dat_o),
.src_adr_o (src_b.adr), .src_adr_o (src_b.adr),
.src_sel_o (src_b.sel), .src_sel_o (src_b.sel),
.src_cyc_o (src_b.cyc), .src_cyc_o (src_b.cyc),
...@@ -199,7 +199,8 @@ module ep2ep_wrapper ...@@ -199,7 +199,8 @@ module ep2ep_wrapper
.src_we_o (src_b.we), .src_we_o (src_b.we),
.src_stall_i (src_b.stall), .src_stall_i (src_b.stall),
.src_ack_i (src_b.ack), .src_ack_i (src_b.ack),
.src_err_i (src_b.err),
.snk_dat_i (snk_b.dat_i[15:0]), .snk_dat_i (snk_b.dat_i[15:0]),
.snk_adr_i (snk_b.adr[1:0]), .snk_adr_i (snk_b.adr[1:0]),
.snk_sel_i (snk_b.sel[1:0]), .snk_sel_i (snk_b.sel[1:0]),
...@@ -230,6 +231,9 @@ module ep2ep_wrapper ...@@ -230,6 +231,9 @@ module ep2ep_wrapper
.wb_ack_o (sys_b.ack) .wb_ack_o (sys_b.ack)
); );
task ep_init(CWishboneAccessor acc); task ep_init(CWishboneAccessor acc);
acc.set_mode(CLASSIC); acc.set_mode(CLASSIC);
acc.write(`ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN); acc.write(`ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN);
......
testbench/wr_minic_with_ep/main.sv
View file @ ab824629
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
`include "ep2ep_wrapper.svh" `include "ep2ep_wrapper.svh"
module main; module main;
reg clk_ref = 1'b0; reg clk_ref = 1'b0;
...@@ -15,8 +16,8 @@ module main; ...@@ -15,8 +16,8 @@ module main;
reg rst_n = 1'b0; reg rst_n = 1'b0;
always #4ns clk_ref <= ~clk_ref; always #3900ps clk_ref <= ~clk_ref;
always@(posedge clk_ref) clk_sys <= ~clk_sys; always #8ns clk_sys <= ~clk_sys;
initial begin initial begin
...@@ -113,15 +114,15 @@ module main; ...@@ -113,15 +114,15 @@ module main;
.src_err_i (minic2ep.slave.err), .src_err_i (minic2ep.slave.err),
.src_ack_i (minic2ep.slave.ack), .src_ack_i (minic2ep.slave.ack),
.snk_dat_i (ep2minic.master.dat_o), .snk_dat_i (ep2minic.dat_o),
.snk_adr_i (ep2minic.master.adr), .snk_adr_i (ep2minic.adr),
.snk_sel_i (ep2minic.master.sel), .snk_sel_i (ep2minic.sel),
.snk_cyc_i (ep2minic.master.cyc), .snk_cyc_i (ep2minic.cyc),
.snk_stb_i (ep2minic.master.stb), .snk_stb_i (ep2minic.stb),
.snk_we_i (ep2minic.master.we), .snk_we_i (ep2minic.we),
.snk_stall_o (ep2minic.master.stall), .snk_stall_o (ep2minic.stall),
.snk_err_o (ep2minic.master.err), .snk_err_o (ep2minic.err),
.snk_ack_o (ep2minic.master.ack), .snk_ack_o (ep2minic.ack),
.txtsu_port_id_i (5'b0), .txtsu_port_id_i (5'b0),
.txtsu_frame_id_i (16'b0), .txtsu_frame_id_i (16'b0),
...@@ -129,6 +130,7 @@ module main; ...@@ -129,6 +130,7 @@ module main;
.txtsu_valid_i (1'b0), .txtsu_valid_i (1'b0),
.txtsu_ack_o (), .txtsu_ack_o (),
.wb_cyc_i (U_sys_bus_master.cyc), .wb_cyc_i (U_sys_bus_master.cyc),
.wb_stb_i (U_sys_bus_master.stb), .wb_stb_i (U_sys_bus_master.stb),
...@@ -180,7 +182,7 @@ module main; ...@@ -180,7 +182,7 @@ module main;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE | EthPacketGenerator::TX_OOB | EthPacketGenerator::EVEN_LENGTH) ; gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE | EthPacketGenerator::TX_OOB | EthPacketGenerator::EVEN_LENGTH) ;
gen.set_template(tmpl); gen.set_template(tmpl);
gen.set_size(60,1500); gen.set_size(100,200);
for(i=0;i<n_packets;i++) for(i=0;i<n_packets;i++)
begin begin
...@@ -225,7 +227,7 @@ module main; ...@@ -225,7 +227,7 @@ module main;
EthPacketGenerator gen = new; EthPacketGenerator gen = new;
EthPacket pkt, tmpl; EthPacket pkt, tmpl;
EthPacket txed[$]; EthPacket txed[$];
int i; int i, cnt;
...@@ -245,10 +247,9 @@ module main; ...@@ -245,10 +247,9 @@ module main;
minic.init(); minic.init();
test_tx_path(10000, minic, sink); // test_tx_path(3000, minic, sink);
/* -----\/----- EXCLUDED -----\/-----
tmpl = new; tmpl = new;
tmpl.src = '{1,2,3,4,5,6}; tmpl.src = '{1,2,3,4,5,6};
...@@ -256,11 +257,15 @@ module main; ...@@ -256,11 +257,15 @@ module main;
tmpl.has_smac = 1; tmpl.has_smac = 1;
tmpl.is_q = 0; tmpl.is_q = 0;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /-*| EthPacketGenerator::RX_OOB*-/) ; gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_template(tmpl); gen.set_template(tmpl);
gen.set_size(60,1500); gen.set_size(60,150);
#10us;
cnt = 0;
fork fork
forever forever
begin begin
...@@ -272,6 +277,8 @@ module main; ...@@ -272,6 +277,8 @@ module main;
EthPacket rxp, sent; EthPacket rxp, sent;
minic.recv(rxp); minic.recv(rxp);
sent = txed.pop_front(); sent = txed.pop_front();
cnt ++;
if(!sent.equal(rxp, EthPacket::CMP_OOB)) if(!sent.equal(rxp, EthPacket::CMP_OOB))
begin begin
sent.dump(); sent.dump();
...@@ -279,6 +286,10 @@ module main; ...@@ -279,6 +286,10 @@ module main;
$stop; $stop;
end end
else
$display("Rx: %x cnt %d", rxp.ethertype, cnt);
end end
...@@ -287,7 +298,7 @@ module main; ...@@ -287,7 +298,7 @@ module main;
// forever // forever
begin begin
for(i=0;i<100;i++) for(i=0;i<205;i++)
begin begin
pkt = gen.gen(); pkt = gen.gen();
src.send(pkt); src.send(pkt);
...@@ -312,7 +323,6 @@ module main; ...@@ -312,7 +323,6 @@ module main;
-----/\----- EXCLUDED -----/\----- */
end // initial begin end // initial begin
......
testbench/wr_minic_with_ep/wave.do
View file @ ab824629
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /main/minic2ep/g_data_width add wave -noupdate /main/DUT/mem_data_o
add wave -noupdate /main/minic2ep/g_addr_width add wave -noupdate /main/DUT/mem_addr_o
add wave -noupdate /main/minic2ep/adr add wave -noupdate /main/DUT/mem_data_i
add wave -noupdate /main/minic2ep/dat_o add wave -noupdate /main/DUT/mem_wr_o
add wave -noupdate /main/minic2ep/dat_i
add wave -noupdate /main/minic2ep/sel
add wave -noupdate /main/minic2ep/ack
add wave -noupdate /main/minic2ep/stall
add wave -noupdate /main/minic2ep/err
add wave -noupdate /main/minic2ep/rty
add wave -noupdate /main/minic2ep/cyc
add wave -noupdate /main/minic2ep/stb
add wave -noupdate /main/minic2ep/we
add wave -noupdate -divider sink
add wave -noupdate /main/U_wrf_sink/g_addr_width
add wave -noupdate /main/U_wrf_sink/g_data_width
add wave -noupdate /main/U_wrf_sink/clk_i
add wave -noupdate /main/U_wrf_sink/rst_n_i
add wave -noupdate /main/U_wrf_sink/adr
add wave -noupdate /main/U_wrf_sink/dat_i
add wave -noupdate /main/U_wrf_sink/sel
add wave -noupdate /main/U_wrf_sink/dat_o
add wave -noupdate /main/U_wrf_sink/ack
add wave -noupdate /main/U_wrf_sink/stall
add wave -noupdate /main/U_wrf_sink/err
add wave -noupdate /main/U_wrf_sink/rty
add wave -noupdate /main/U_wrf_sink/cyc
add wave -noupdate /main/U_wrf_sink/stb
add wave -noupdate /main/U_wrf_sink/we
add wave -noupdate /main/U_wrf_sink/last_access_t
add wave -noupdate /main/U_wrf_sink/cyc_prev
add wave -noupdate /main/U_wrf_sink/trans_index
add wave -noupdate /main/U_wrf_sink/first_transaction
add wave -noupdate /main/U_wrf_sink/settings
add wave -noupdate /main/U_wrf_sink/cyc_start
add wave -noupdate /main/U_wrf_sink/cyc_end
add wave -noupdate /main/U_wrf_sink/clk_i
add wave -noupdate /main/U_wrf_sink/rst_n_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_vlans
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_dpi_classifier
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_rtu
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_with_rx_buffer
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/g_rx_buffer_size
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/clk_sys_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/clk_rx_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rst_n_sys_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rst_n_rx_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fab_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fifo_almostfull_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_busy_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_wb_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_wb_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_pause_p_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_pause_delay_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fc_buffer_occupation_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rmon_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/regs_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_rq_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_full_i
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rtu_rq_valid_o
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/state
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/gap_cntr
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/counter
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/rxdata_saved
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/next_hdr
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/is_pause
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/data_firstword
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/flush_stall
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/stb_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fab_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/dreq_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ack_count
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/src_out_int
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/tmp_sel
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/tmp_dat
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/fab_pipe
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/dreq_pipe
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_done
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_is_hp
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_is_pause
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/ematch_pause_quanta
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_pclass
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_drop
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pfilter_done
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_tclass
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_vid
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/vlan_tag_done
add wave -noupdate /main/U_Eps/EP_A/U_Rx_Path/pcs_fifo_almostfull
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {62482422150 fs} 0} WaveRestoreCursors {{Cursor 1} {70088000000 fs} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 183
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
configure wave -signalnamewidth 1 configure wave -signalnamewidth 1
...@@ -104,4 +20,4 @@ configure wave -griddelta 40 ...@@ -104,4 +20,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {54279296390 fs} {70685547910 fs} WaveRestoreZoom {0 fs} {1050 us}
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