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White Rabbit core collection
Commits
a31dc9eb
Commit
a31dc9eb
authored
Nov 09, 2018
by
Grzegorz Daniluk
Browse files
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Plain Diff
add rx preamble shrinkage support
parent
b6dfc740
Expand all
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Showing
10 changed files
with
250 additions
and
79 deletions
+250
-79
endpoint_pkg.vhd
modules/wr_endpoint/endpoint_pkg.vhd
+15
-3
endpoint_private_pkg.vhd
modules/wr_endpoint/endpoint_private_pkg.vhd
+12
-5
ep_1000basex_pcs.vhd
modules/wr_endpoint/ep_1000basex_pcs.vhd
+8
-4
ep_rtu_header_extract.vhd
modules/wr_endpoint/ep_rtu_header_extract.vhd
+8
-1
ep_rx_path.vhd
modules/wr_endpoint/ep_rx_path.vhd
+5
-1
ep_rx_pcs_16bit.vhd
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+164
-53
ep_rx_wb_master.vhd
modules/wr_endpoint/ep_rx_wb_master.vhd
+2
-1
ep_tx_pcs_8bit.vhd
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
+22
-5
wr_endpoint.vhd
modules/wr_endpoint/wr_endpoint.vhd
+10
-4
xwr_endpoint.vhd
modules/wr_endpoint/xwr_endpoint.vhd
+4
-2
No files found.
modules/wr_endpoint/endpoint_pkg.vhd
View file @
a31dc9eb
...
...
@@ -148,6 +148,14 @@ package endpoint_pkg is
rx
:
t_dbg_ep_rxpcs
;
end
record
;
type
t_dbg_rtu_extract
is
record
in_packet
:
std_logic
;
in_header
:
std_logic
;
rtu_rq_valid_basic
:
std_logic
;
rtu_rq_valid_tagged
:
std_logic
;
rtu_rq_abort
:
std_logic
;
end
record
;
type
t_dbg_ep_rxpath
is
record
fab_pipe
:
t_fab_pipe
(
9
downto
0
);
dreq_pipe
:
std_logic_vector
(
9
downto
0
);
...
...
@@ -155,6 +163,7 @@ package endpoint_pkg is
pcs_fifo_empty
:
std_logic
;
pcs_fifo_full
:
std_logic
;
rxbuf_full
:
std_logic
;
rtu_extract
:
t_dbg_rtu_extract
;
end
record
;
type
t_dbg_ep
is
record
...
...
@@ -186,7 +195,8 @@ package endpoint_pkg is
g_with_packet_injection
:
boolean
:
=
false
;
g_use_new_rxcrc
:
boolean
:
=
false
;
g_use_new_txcrc
:
boolean
:
=
false
;
g_with_stop_traffic
:
boolean
:
=
false
);
g_with_stop_traffic
:
boolean
:
=
false
;
g_ep_idx
:
integer
:
=
0
);
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -297,7 +307,8 @@ package endpoint_pkg is
g_with_packet_injection
:
boolean
:
=
false
;
g_use_new_rxcrc
:
boolean
:
=
false
;
g_use_new_txcrc
:
boolean
:
=
false
;
g_with_stop_traffic
:
boolean
:
=
false
);
g_with_stop_traffic
:
boolean
:
=
false
;
g_ep_idx
:
integer
:
=
0
);
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -403,7 +414,8 @@ package endpoint_pkg is
stop_traffic_i
:
in
std_logic
:
=
'0'
;
dbg_tx_pcs_wr_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
dbg_tx_pcs_rd_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
nice_dbg_o
:
out
t_dbg_ep
);
nice_dbg_o
:
out
t_dbg_ep
;
preamble_shrinkage
:
in
std_logic
:
=
'0'
);
end
component
;
constant
c_xwr_endpoint_sdb
:
t_sdb_device
:
=
(
...
...
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @
a31dc9eb
...
...
@@ -116,7 +116,8 @@ package endpoint_private_pkg is
component
ep_1000basex_pcs
generic
(
g_simulation
:
boolean
;
g_16bit
:
boolean
);
g_16bit
:
boolean
;
g_ep_idx
:
integer
);
port
(
rst_sys_n_i
:
in
std_logic
;
rst_txclk_n_i
:
in
std_logic
;
...
...
@@ -163,7 +164,8 @@ package endpoint_private_pkg is
mdio_ready_o
:
out
std_logic
;
dbg_tx_pcs_wr_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
dbg_tx_pcs_rd_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
nice_dbg_o
:
out
t_dbg_ep_pcs
);
nice_dbg_o
:
out
t_dbg_ep_pcs
;
preamble_shrinkage
:
in
std_logic
);
end
component
;
component
ep_tx_pcs_8bit
...
...
@@ -186,7 +188,8 @@ package endpoint_private_pkg is
phy_tx_data_o
:
out
std_logic_vector
(
7
downto
0
);
phy_tx_k_o
:
out
std_logic
;
phy_tx_disparity_i
:
in
std_logic
;
phy_tx_enc_err_i
:
in
std_logic
);
phy_tx_enc_err_i
:
in
std_logic
;
preamble_shrinkage
:
in
std_logic
:
=
'0'
);
end
component
;
component
ep_tx_pcs_16bit
...
...
@@ -250,7 +253,8 @@ package endpoint_private_pkg is
component
ep_rx_pcs_16bit
generic
(
g_simulation
:
boolean
);
g_simulation
:
boolean
;
g_ep_idx
:
integer
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -517,7 +521,8 @@ package endpoint_private_pkg is
rtu_full_i
:
in
std_logic
;
rtu_rq_abort_o
:
out
std_logic
;
rtu_rq_valid_o
:
out
std_logic
;
rxbuf_full_i
:
in
std_logic
);
rxbuf_full_i
:
in
std_logic
;
nice_dbg_o
:
out
t_dbg_rtu_extract
);
end
component
;
component
ep_rx_early_address_match
...
...
@@ -620,6 +625,7 @@ package endpoint_private_pkg is
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
stop_traffic_i
:
in
std_logic
:
=
'0'
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
src_wb_i
:
in
t_wrf_source_in
;
...
...
@@ -675,6 +681,7 @@ package endpoint_private_pkg is
clk_rx_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
rst_n_rx_i
:
in
std_logic
;
stop_traffic_i
:
in
std_logic
;
pcs_fab_i
:
in
t_ep_internal_fabric
;
pcs_fifo_almostfull_o
:
out
std_logic
;
pcs_busy_i
:
in
std_logic
;
...
...
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @
a31dc9eb
...
...
@@ -63,7 +63,8 @@ entity ep_1000basex_pcs is
g_simulation
:
boolean
;
-- PCS datapath width selection: true = 16-bit (Virtex-6), false = 8-bit
-- (Spartan-6 or TBI).
g_16bit
:
boolean
);
g_16bit
:
boolean
;
g_ep_idx
:
integer
);
port
(
...
...
@@ -195,7 +196,8 @@ entity ep_1000basex_pcs is
dbg_tx_pcs_wr_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
dbg_tx_pcs_rd_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
nice_dbg_o
:
out
t_dbg_ep_pcs
);
nice_dbg_o
:
out
t_dbg_ep_pcs
;
preamble_shrinkage
:
in
std_logic
);
end
ep_1000basex_pcs
;
...
...
@@ -295,7 +297,8 @@ begin -- rtl
U_RX_PCS
:
ep_rx_pcs_16bit
generic
map
(
g_simulation
=>
g_simulation
)
g_simulation
=>
g_simulation
,
g_ep_idx
=>
g_ep_idx
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
pcs_reset_n
,
...
...
@@ -366,7 +369,8 @@ begin -- rtl
phy_tx_data_o
=>
serdes_tx_data_o
(
7
downto
0
),
phy_tx_k_o
=>
serdes_tx_k_o
(
0
),
phy_tx_disparity_i
=>
serdes_tx_disparity_i
,
phy_tx_enc_err_i
=>
serdes_tx_enc_err_i
phy_tx_enc_err_i
=>
serdes_tx_enc_err_i
,
preamble_shrinkage
=>
preamble_shrinkage
);
U_RX_PCS
:
ep_rx_pcs_8bit
...
...
modules/wr_endpoint/ep_rtu_header_extract.vhd
View file @
a31dc9eb
...
...
@@ -61,7 +61,8 @@ entity ep_rtu_header_extract is
rtu_full_i
:
in
std_logic
;
rtu_rq_abort_o
:
out
std_logic
;
rtu_rq_valid_o
:
out
std_logic
;
rxbuf_full_i
:
in
std_logic
rxbuf_full_i
:
in
std_logic
;
nice_dbg_o
:
out
t_dbg_rtu_extract
);
end
ep_rtu_header_extract
;
...
...
@@ -201,5 +202,11 @@ begin -- rtl
rtu_rq_o
.
has_prio
<=
vlan_is_tagged_i
;
rtu_rq_valid_o
<=
rtu_rq_valid_out
and
not
snk_fab_i
.
ERROR
;
rtu_rq_o
.
hash
<=
(
others
=>
'0'
);
nice_dbg_o
.
in_packet
<=
in_packet
;
nice_dbg_o
.
in_header
<=
in_header
;
nice_dbg_o
.
rtu_rq_valid_basic
<=
rtu_rq_valid_basic
;
nice_dbg_o
.
rtu_rq_valid_tagged
<=
rtu_rq_valid_tagged
;
nice_dbg_o
.
rtu_rq_abort
<=
rtu_rq_abort
;
end
rtl
;
modules/wr_endpoint/ep_rx_path.vhd
View file @
a31dc9eb
...
...
@@ -75,6 +75,8 @@ entity ep_rx_path is
rst_n_sys_i
:
in
std_logic
;
rst_n_rx_i
:
in
std_logic
;
stop_traffic_i
:
in
std_logic
;
-- physical coding sublayer (PCS) interface
pcs_fab_i
:
in
t_ep_internal_fabric
;
pcs_fifo_almostfull_o
:
out
std_logic
;
...
...
@@ -394,7 +396,8 @@ begin -- behavioral
rtu_full_i
=>
rtu_full_i
,
rtu_rq_abort_o
=>
rtu_rq_abort_o
,
rtu_rq_valid_o
=>
rtu_rq_valid
,
rxbuf_full_i
=>
rxbuf_full
);
rxbuf_full_i
=>
rxbuf_full
,
nice_dbg_o
=>
nice_dbg_o
.
rtu_extract
);
gen_with_rx_buffer
:
if
g_with_rx_buffer
generate
U_Rx_Buffer
:
ep_rx_buffer
...
...
@@ -445,6 +448,7 @@ begin -- behavioral
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
stop_traffic_i
=>
stop_traffic_i
,
snk_fab_i
=>
fab_pipe
(
9
),
snk_dreq_o
=>
dreq_pipe
(
9
),
src_wb_i
=>
src_wb_i
,
...
...
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @
a31dc9eb
This diff is collapsed.
Click to expand it.
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @
a31dc9eb
...
...
@@ -56,6 +56,7 @@ entity ep_rx_wb_master is
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
stop_traffic_i
:
in
std_logic
:
=
'0'
;
-- physical coding sublayer (PCS) interface
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
...
...
@@ -157,7 +158,7 @@ begin -- behavioral
state
<=
FLUSH_STALL
;
end
if
;
if
(
snk_fab_i
.
eof
=
'1'
)
then
if
(
snk_fab_i
.
eof
=
'1'
or
stop_traffic_i
=
'1'
)
then
state
<=
FINISH_CYCLE
;
end
if
;
...
...
modules/wr_endpoint/ep_tx_pcs_8bit.vhd
View file @
a31dc9eb
...
...
@@ -119,7 +119,9 @@ entity ep_tx_pcs_8bit is
phy_tx_data_o
:
out
std_logic_vector
(
7
downto
0
);
phy_tx_k_o
:
out
std_logic
;
phy_tx_disparity_i
:
in
std_logic
;
phy_tx_enc_err_i
:
in
std_logic
phy_tx_enc_err_i
:
in
std_logic
;
preamble_shrinkage
:
in
std_logic
:
=
'0'
);
end
ep_tx_pcs_8bit
;
...
...
@@ -162,6 +164,9 @@ architecture behavioral of ep_tx_pcs_8bit is
signal
mdio_mcr_pdown_synced
:
std_logic
;
signal
an_tx_en_synced
:
std_logic
;
signal
s_one
:
std_logic
:
=
'1'
;
signal
sh_preamble_sent
:
std_logic
;
begin
U_sync_pcs_busy_o
:
gc_sync_ffs
...
...
@@ -280,7 +285,7 @@ begin
tx_odd_length
<=
'0'
;
tx_rdreq_toggle
<=
'0'
;
rmon_tx_underrun
<=
'0'
;
sh_preamble_sent
<=
'0'
;
else
case
tx_state
is
...
...
@@ -294,6 +299,7 @@ begin
tx_state
<=
TX_IDLE
;
fifo_rd
<=
'0'
;
fifo_ready
<=
fifo_rd
;
sh_preamble_sent
<=
'0'
;
-------------------------------------------------------------------------------
-- State IDLE: sends the second code of the /I/ sequence with proper disparity\
...
...
@@ -304,6 +310,7 @@ begin
-- make sure is't long enough to trigger the event counter
rmon_tx_underrun
<=
'0'
;
tx_error
<=
'0'
;
sh_preamble_sent
<=
'0'
;
-- endpoint wants to send Config_Reg
if
(
an_tx_en_synced
=
'1'
)
then
...
...
@@ -315,7 +322,12 @@ begin
elsif
(
fifo_fab
.
sof
=
'1'
and
fifo_ready
=
'1'
and
tx_cntr
=
"0000"
)
then
fifo_rd
<=
'1'
;
tx_state
<=
TX_SPD
;
tx_cntr
<=
"0101"
;
if
(
preamble_shrinkage
=
'0'
)
then
-- generate preamble shrinkage
tx_cntr
<=
"0101"
;
else
sh_preamble_sent
<=
'1'
;
tx_cntr
<=
"0100"
;
end
if
;
-- host requested a calibration pattern
elsif
(
mdio_wr_spec_tx_cal_i
=
'1'
)
then
...
...
@@ -453,8 +465,13 @@ begin
tx_rdreq_toggle
<=
not
tx_rdreq_toggle
;
-- handle the end of frame both for even- and odd-length frames
tx_odd_length
<=
fifo_fab
.
bytesel
;
-- handle the end of frame both for even- and odd-length frames,
-- including preamble shrinkage
if
(
sh_preamble_sent
=
'0'
)
then
tx_odd_length
<=
fifo_fab
.
bytesel
;
else
tx_odd_length
<=
not
fifo_fab
.
bytesel
;
end
if
;
if
(
fifo_fab
.
eof
=
'1'
and
(
tx_rdreq_toggle
=
'0'
or
(
tx_rdreq_toggle
=
'1'
and
fifo_fab
.
bytesel
=
'1'
)))
then
tx_state
<=
TX_EPD
;
...
...
modules/wr_endpoint/wr_endpoint.vhd
View file @
a31dc9eb
...
...
@@ -74,7 +74,8 @@ entity wr_endpoint is
g_with_packet_injection
:
boolean
:
=
false
;
g_use_new_rxcrc
:
boolean
:
=
false
;
g_use_new_txcrc
:
boolean
:
=
false
;
g_with_stop_traffic
:
boolean
:
=
false
g_with_stop_traffic
:
boolean
:
=
false
;
g_ep_idx
:
integer
:
=
0
);
port
(
...
...
@@ -303,7 +304,8 @@ entity wr_endpoint is
dbg_tx_pcs_wr_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
dbg_tx_pcs_rd_count_o
:
out
std_logic_vector
(
5
+
4
downto
0
);
nice_dbg_o
:
out
t_dbg_ep
nice_dbg_o
:
out
t_dbg_ep
;
preamble_shrinkage
:
in
std_logic
);
end
wr_endpoint
;
...
...
@@ -488,7 +490,8 @@ begin
U_PCS_1000BASEX
:
ep_1000basex_pcs
generic
map
(
g_simulation
=>
g_simulation
,
g_16bit
=>
g_pcs_16bit
)
g_16bit
=>
g_pcs_16bit
,
g_ep_idx
=>
g_ep_idx
)
port
map
(
rst_sys_n_i
=>
rst_sys_n_i
,
rst_rxclk_n_i
=>
rst_rxclk_n_i
,
...
...
@@ -544,7 +547,8 @@ begin
mdio_ready_o
=>
regs_towb_ep
.
mdio_asr_ready_i
,
dbg_tx_pcs_wr_count_o
=>
dbg_tx_pcs_wr_count_o
,
dbg_tx_pcs_rd_count_o
=>
dbg_tx_pcs_rd_count_o
,
nice_dbg_o
=>
nice_dbg_o
.
pcs
);
nice_dbg_o
=>
nice_dbg_o
.
pcs
,
preamble_shrinkage
=>
preamble_shrinkage
);
-------------------------------------------------------------------------------
...
...
@@ -629,6 +633,8 @@ begin
rst_n_sys_i
=>
rst_n_rx_resync_sys
,
rst_n_rx_i
=>
rst_n_rx
,
stop_traffic_i
=>
stop_traffic_i
,
pcs_fab_i
=>
rxpath_fab
,
pcs_fifo_almostfull_o
=>
rxpcs_fifo_almostfull
,
pcs_busy_i
=>
rxpcs_busy
,
...
...
modules/wr_endpoint/xwr_endpoint.vhd
View file @
a31dc9eb
...
...
@@ -65,7 +65,8 @@ entity xwr_endpoint is
g_with_packet_injection
:
boolean
:
=
false
;
g_use_new_rxcrc
:
boolean
:
=
false
;
g_use_new_txcrc
:
boolean
:
=
false
;
g_with_stop_traffic
:
boolean
:
=
false
g_with_stop_traffic
:
boolean
:
=
false
;
g_ep_idx
:
integer
);
port
(
...
...
@@ -319,7 +320,8 @@ begin
g_with_packet_injection
=>
g_with_packet_injection
,
g_use_new_rxcrc
=>
g_use_new_rxcrc
,
g_use_new_txcrc
=>
g_use_new_txcrc
,
g_with_stop_traffic
=>
g_with_stop_traffic
)
g_with_stop_traffic
=>
g_with_stop_traffic
,
g_ep_idx
=>
g_ep_idx
)
port
map
(
clk_ref_i
=>
clk_ref_i
,
clk_sys_i
=>
clk_sys_i
,
...
...
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